DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
Applicant's 12/4/2023 Preliminary Amendment to: 1. Amend the instant Specification. 2. Amend the Abstract. 3. Amend the Claims is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/4/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claims Status
Claims 1-10 are currently pending and being examined. Claims 3, 5-6 and 8-10 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 is rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the converted electric power" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "the converted electric power" in line 3, will be interpreted to read as "the converted input electric power".
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over KAJI et al (US 2020/0020622 A1, hereafter Kaji) and HIGASHI (US 2020/0266129 A1, hereafter Higashi) and Kwon et al (US 2022/0328376 A1, hereafter Kwon).
Re Claim 1, Kaji discloses in FIG. 1 a semiconductor module (101) comprising:
a semiconductor chip (right 4; [0024]);
an insulating substrate (2; [0025]) including a main circuit pattern (right 2P; [0025]) electrically connected ([0033]) to the semiconductor chip (right 4) and an insulating layer (2D; [0025]) sandwiching (covering above and below) the main circuit pattern (right 2P) together with the semiconductor chip (right 4);
a relay board (right 3P; [0024]) to sandwich (cover above and below) the semiconductor chip (right 4) together with the main circuit pattern (right 2P) in a sandwiching direction (vertically) in which the insulating layer (2D) and the semiconductor chip (right 4) sandwich (cover above and below) the main circuit pattern (right 2P), the relay board (right 3P) being electrically connected ([0037]-[0038]) to the main circuit pattern (right 2P) through the semiconductor chip (right 4).
A. Kaji fails to disclose and a heat-dissipating component sandwiched between the insulating substrate (2) and the relay board (right 3P) in the sandwiching direction (vertically), wherein the heat-dissipating component is electrically insulated from the semiconductor chip (right 4) and the main circuit pattern (right 2P), and the main circuit pattern (right 2P) at least partially surrounds the heat-dissipating component on the insulating layer (2D).
However,
Higashi discloses in FIGS. 4A-4B (with references to FIG. 1) a semiconductor module (1) comprising: a heat-dissipating component (86; [0068]-[0069]) sandwiched between (covered above and below) an insulating substrate (2; [0068]) and a relay board (80; [0068]) in a sandwiching direction (vertically), and a main circuit pattern (22 as in FIG. 1; [0021]) at least partially surrounds (is adjacent to on one side as in FIG. 1) the heat-dissipating component (86) on an insulating layer (21; [0066]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kaji by adding the heat-dissipating component and its associated structure (see inserted figure below) as disclosed by Higashi, producing a heat-dissipating component sandwiched between the insulating substrate (2) and the relay board (right 3P) in the sandwiching direction (vertically), and the main circuit pattern (right 2P) at least partially surrounds the heat-dissipating component on the insulating layer (2D), where the heat from the semiconductor chip can be dissipated to the insulating substrate side. Therefore, excessive heat generation by the semiconductor chips of the semiconductor module can be prevented (Higashi; [0045]).
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For the record, the inserted figure (annotated FIG. 8 of Kaji) depicts the heat-dissipating components (85/86/87) of Higashi added to the semiconductor module of Kaji. More specifically, heat-dissipating component (86) of Higashi is sandwiched between an insulating substrate (2) and a relay board (80) in a sandwiching direction (vertically), such that a main circuit pattern (22) at least partially surrounds (is adjacent to on one side) the heat-dissipating component (86) on an insulating layer (21).
B. Kaji and Higashi fail to disclose wherein the heat-dissipating component (Higashi: 86) is electrically insulated from the semiconductor chip (Kaji: right 4) and the main circuit pattern (Kaji: right 2P).
However,
Kwon discloses in FIG. 6A a semiconductor module (IC package) comprising: heat-dissipating components (618; [0005] and [0054]) made of conductive, dielectric or ceramic materials ([0054]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kaji and Higashi by using a dielectric or ceramic material, as disclosed by Kwon, as the material for the heat-dissipating component of Kaji and Higashi, wherein the heat-dissipating component (Higashi: 86) is electrically insulated from the semiconductor chip (Kaji: right 4) and the main circuit pattern (Kaji: right 2P), which prevents short-circuits between adjacent semiconductor chips of the semiconductor module.
Re Claim 2, Kaji discloses the semiconductor module according to claim 1.
But, fails to disclose wherein the insulating substrate (2) includes a separated pattern that is disposed on a same side as the main circuit pattern (right 2P) with respect to the insulating layer (2D) and that is electrically insulated from the main circuit pattern (right 2P), and the heat-dissipating component is sandwiched between the separated pattern and the relay board (right 3P).
However, Higashi discloses a separated pattern (26; [0069] and see inserted figure above) that is disposed on a same side (upper plane) as the main circuit pattern (22) with respect to the insulating layer (21) and that is electrically insulated ([0024]) from the main circuit pattern (22), such that the heat-dissipating component (86) is sandwiched between (see inserted figure above) the separated pattern (26) and the relay board (right 3P), as would be part of the heat-dissipating component discussed for claim 1.
Re Claim 3, Kaji discloses the semiconductor module according to claim 1, further comprising an electrode terminal (8; [0043]), wherein the electrode terminal (8) is connected ([0043]) to the relay board (right 3P) and protrudes (extends) from the relay board (right 3P) in a direction opposite to (above) the insulating substrate (2).
Re Claim 4, Kaji and Higashi disclose the semiconductor module according to claim 3, wherein the electrode terminal (Kaji: 8) and the heat-dissipating component (higashi: 86) sandwich (cover above/below; see inserted figure above) the relay board (right 3P), as would be part of the heat-dissipating component discussed for claim 1.
Re Claim 5, Kaji discloses the semiconductor module according to claim 1.
But, fails to disclose wherein the heat-dissipating component includes a first member and a second member, the first member and the second member are spaced from each other, and the relay board is connected to the insulating substrate through the first member and the second member.
However, Higashi would render these limitations by using heat-dissipating component (77; [0065]-[0066]) as a second member, and configuring heat-dissipating structure (76/77/78) as in heat-dissipating structure (85/86/87) in the inserted figure above, wherein the heat-dissipating component includes a first member and a second member, the first member and the second member are spaced from each other, and the relay board is connected to the insulating substrate through the first member and the second member. Therefore, excessive heat generation by the semiconductor chips of the semiconductor module can be prevented (Higashi; [0045]) as discussed for claim 1.
Re Claim 6, Kaji and Higashi disclose the semiconductor module according to claim 1, wherein the heat-dissipating component (higashi: 86) includes a first surface (lower plane) joined to the insulating substrate (Kaji: 2) and a second surface (upper plane) joined (by 85; see inserted figure above) to the relay board (Kaji: right 3P).
But, fails to disclose and the second surface (upper plane) has a larger area than the first surface (lower plane).
However, Kwon discloses in the embodiments of FIGS. 6C and 6D heat-dissipating components (632/636/642/644; [0056]-[0057]) with first surfaces and second surfaces of different areas ([0056]-[0057]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kaji and Higashi by using the teachings of heat-dissipating components with first surfaces and second surfaces of different areas, as disclosed by Kwon, to configuration (through routine experimentation; MPEP 2144.05) the second surface (upper plane) to have a larger area than the first surface (lower plane), to dissipate the heat generated at certain local hot spots at a faster rate so as to efficiently carry away the heat from semiconductor chip (Kwon; [0056]) and/or to provide additional heat dissipating area to assist dissipating heat at certain local hot spots at a greater heat dissipating rate or efficiency (Kwon; [0057]).
Re Claim 7, Kaji discloses the semiconductor module according to claim 1, wherein the insulating substrate (2) includes a base plate (2C; [0025]) disposed on an opposite side (below) of the main circuit pattern (right 2P) from the semiconductor chip (right 4).
But, fails to disclose and the heat-dissipating component is directly connected to the base plate (2C).
However, Higashi would render these limitations obvious since heat-dissipating component (87), which extends from heat-dissipating component (86), is directly connected to (physically touches; see inserted figure above) the base plate (2C), as would be part of the heat-dissipating component discussed for claim 1.
Re Claim 8, Kaji discloses the semiconductor module according to claim 1.
But, fails to disclose wherein the heat-dissipating component is a metallic column.
However, Higashi discloses the heat-dissipating component (86) is column, and Kwon discloses the heat-dissipating component can be a metallic material ([0054]) to render these limitations obvious, as would be part of the heat-dissipating components discussed for claim 1.
Re Claim 9, Kaji discloses the semiconductor module according to claim 1.
But, fails to disclose wherein the heat-dissipating component is constituted from a semiconductor element having a structure that is the same as or different from that of the semiconductor chip (right 4).
However, Kwon discloses the heat-dissipating component can be semiconductor materials ([0054]), and semiconductor chips (202/252/300) made of silicon ([0040]) to render these limitations obvious, such that the heat-dissipating component is constituted from a semiconductor element (silicon) having a structure that is the same as or different from that of the semiconductor chip (silicon right 4), as would be part of the heat-dissipating components discussed for claim 1.
Re Claim 10, Kaji discloses in FIG. 10 a power converter ([0080]) comprising: a main converter circuit (2010; [0081]) including the semiconductor module (101 modified Higashi and Kwon) according to claim 1 (see above), to convert input electric power (DC power from power supply 1000; [0081]) and output (to load 3000; [0081]) the converted input electric power (AC power; [0081]); and a control circuit (2030; [0081]) to output a control signal ([0081]) for controlling the main converter circuit ([0081]) to the main converter circuit ([0081]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892