Prosecution Insights
Last updated: October 02, 2026
Application No. 18/566,939

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC EQUIPMENT

Non-Final OA §102
Filed
Dec 04, 2023
Priority
Jun 11, 2021 — JP 2021-097809 +1 more
Examiner
GEYER, SCOTT B
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
685 granted / 727 resolved
+26.2% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
26 currently pending
Career history
736
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
21.0%
-19.0% vs TC avg
§102
41.5%
+1.5% vs TC avg
§112
24.2%
-15.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 727 resolved cases

Office Action

§102
DETAILED ACTION Election/Restrictions Applicant's election with traverse of Group 1 (claims 1-16) in the reply filed on July 6, 2026 is acknowledged. The traversal is on the grounds that “examination of all of the identified inventions and all of the pending claims would not result in a serious search and/or examination burden”. This is not found persuasive because the restriction requirement clearly outlined a lack of unity, with a reference. Also, search burden is not a consideration in Unity of Invention analysis. The requirement is still deemed proper and is therefore made FINAL. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The references cited within the IDS documents have been considered. IDS document dates: December 4, 2023; December 6, 2023; January 8, 2026. Drawings The drawings are objected to because of informalities as follows: 37 CFR 1.84(g) states, in part: “Margins. The sheets must not contain frames around the sight (i.e., the usable surface), but should have scan target points (i.e., cross-hairs) printed on two catercorner margin corners.” Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 8, 12, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukuoka (US 2018/0033816 A1). As to claim 1, Fukuoka teaches (in figures 1 and 6) a semiconductor device comprising: a photoelectric converting section (112) that generates a charge according to a received light amount; and a transfer transistor (120) that transfers the charge of the photoelectric converting section to a predetermined charge accumulation section, wherein the transfer transistor has a vertical gate electrode (123) including an embedded electrode part embedded in a semiconductor substrate (111), and the embedded electrode part includes an embedded upper electrode and an embedded lower electrode that is arranged on a substrate deep-portion side relative to the embedded upper electrode and that is formed to have an electrode area size, in a plan view, greater than an electrode area size of the embedded upper electrode (see annotated figure below). PNG media_image1.png 657 1056 media_image1.png Greyscale As to claim 8, Fukuoka teaches a predetermined charge accumulation section (i.e. a floating diffusion region, 124) includes a high concentration impurity region (n+). As to claim 12, Fukuoka teaches the semiconductor device includes a solid-state imaging element, and each pixel of the solid-state imaging element includes the photo-electric converting section and the transfer transistor. See figure 1. As to claim 16, Fukuoka teaches a planar shape of the embedded lower electrode is a polygon. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, 12, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 2023/0079156, hereinafter referred to as ‘Chen’). As to claim 1, Chen teaches (in figures 4, 5, and 9) a semiconductor device comprising: a photoelectric converting section (441) that generates a charge according to a received light amount; and a transfer transistor (942) that transfers the charge of the photoelectric converting section to a predetermined charge accumulation section, wherein the transfer transistor has a vertical gate electrode (942) including an embedded electrode part embedded in a semiconductor substrate (410), and the embedded electrode part includes an embedded upper electrode and an embedded lower electrode that is arranged on a substrate deep-portion side relative to the embedded upper electrode and that is formed to have an electrode area size, in a plan view, greater than an electrode area size of the embedded upper electrode (see figures 5 and 9). As to claim 2, Chen teaches the embedded lower electrode is formed as a rectangular tube (see figures 4, 5, and 9). As to claim 12, Chen teaches the semiconductor device includes a solid-state imaging element, and each pixel of the solid-state imaging element includes the photo-electric converting section and the transfer transistor. See figure 4. As to claim 16, Chen teaches a planar shape of the embedded lower electrode is a polygon. See figures 5 and 9. Allowable Subject Matter Claims 3-7, 9-11, 13, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Claim 14 is also objected to as being dependent upon an objected claim.) Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000. /SCOTT B GEYER/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 04, 2023
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751151
DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
2y 9m to grant Granted Sep 29, 2026
Patent 12733223
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Sep 08, 2026
Patent 12733243
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 7m to grant Granted Sep 08, 2026
Patent 12733374
DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME
2y 6m to grant Granted Sep 08, 2026
Patent 12727293
SEMICONDUCTOR LIGHT EMITTING DIODE INCLUDING PASSIVATION LAYER HAVING DIFFERENT THICKNESSES
3y 8m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.2%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 727 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month