DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/30/2026.
However, the common features including as claimed cannot qualify as special technical features as they do not provide a contribution over the prior art rejection as shown below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein an insulation structure is arranged between the first N-type heavily doped region and the first P-type heavily doped region; wherein an insulation structure is arranged between the second P-type heavily doped region and the first N-type heavily doped region; wherein an insulation structure is arranged between the second N-type heavily doped region and the second P-type heavily doped region; wherein an insulation structure is arranged between the fourth N-type heavily doped region and the third N-type heavily doped region”. It is unclear and indefinite if “an insulation structure” is referring to one and the same or not.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over KOO YONG SEO (KR 20140044466 A) (hereinafter Koo) in view of Choi et al. 20200194424.
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Regarding claim 1, fig. 2 of Koo discloses a GGNMOS transistor structure, comprising:
a P-type substrate 500;
a first N-potential well 310, a P-potential well 320, and a second N-potential well 410 that are adjacent and horizontally arranged on the P-type substrate in sequence;
a first P-type heavily doped region 314 arranged above the first N-potential well;
a first N-type heavily doped region 312 arranged above the first N-potential well;
a second P-type heavily doped region 324 arranged above the P-potential well;
a second N-type heavily doped region 322 arranged above the P-potential well;
a third N-type heavily doped region 330 arranged above a boundary between the P-potential well and the second N-potential well;
a fourth N-type heavily doped region 412 arranged above the second N-potential well; and
a gate structure 120a-120b arranged on an upper surface of the P-potential well between the third N-type heavily doped region 330 and the second N-type heavily doped region 322,
wherein the first P-type heavily doped region 314, the first N-type heavily doped region 312, and the fourth N-type heavily doped region 412 are connected to a positive electrode (Anode), and the second P-type heavily doped region 324, the second N-type heavily doped region 322, and the gate structure 120a/b are connected (there exist a physical connection as shown in fig. 1 configuration) to a negative electrode (Cathode).
Koo does not disclose of wherein an insulation structure is arranged between the first N-type heavily doped region and the first P-type heavily doped region; wherein an insulation structure is arranged between the second P-type heavily doped region and the first N-type heavily doped region; wherein an insulation structure is arranged between the second N-type heavily doped region and the second P-type heavily doped region; wherein an insulation structure is arranged between the fourth N-type heavily doped region and the third N-type heavily doped region.
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However, fig. 3 of Choi discloses wherein an insulation structure is arranged between various P-type heavily doped region and various N-type heavily doped region and other various heavily doped regions in order to form electrical isolation between regions.
In view of such teaching, it would have been obvious to form a structure of Koo further comprising wherein an insulation structure is arranged between the first N-type heavily doped region and the first P-type heavily doped region; wherein an insulation structure is arranged between the second P-type heavily doped region and the first N-type heavily doped region; wherein an insulation structure is arranged between the second N-type heavily doped region and the second P-type heavily doped region; wherein an insulation structure is arranged between the fourth N-type heavily doped region and the third N-type heavily doped region such as taught by Choi in order to form electrical isolation between regions.
Regarding claim 2, fig. 2 of Koo discloses wherein the second N-type heavily doped region is used as a source region; and the third N-type heavily doped region and the fourth N-type heavily doped region are used as a drain region (via electrical circuit connection since 412 is connected to node 1 and 312 to 310 to 330 to node 1).
Regarding claim 3, fig. 2 of Koo discloses wherein the first N-potential well 310, the first P-type heavily doped region 314, and the first P-potential well 320 form an equivalent PNP transistor; the first N-potential well, the first P-potential well, and the second N-type heavily doped region 322 form an equivalent NPN transistor; and the second N-potential well 410 forms an equivalent resistor 220.
Regarding claim 4, fig. 2 of Koo discloses wherein the equivalent PNP transistor and the equivalent NPN transistor form a P-N-P-N parasitic thyristor structure.
Regarding claim 5, fig. 2 of Koo discloses wherein upper surfaces of the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, and the fourth N-type heavily doped region are flush.
Regarding claim 6, fig. 2 of Koo discloses wherein junction depths of the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, and the fourth N-type heavily doped region are same.
Regarding claim 7, fig. 2 of Koo discloses wherein the first N-potential well and the second N-potential well are N-type lightly doped; and the P-potential well is P-type lightly doped.
Regarding claim 8, fig. 3 of Choi discloses wherein a depth of each insulation structure is greater than that of various heavily doped regions, and the resulting structure would have been one wherein a depth of each insulation structure is greater than that of the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, and the fourth N-type heavily doped region in order to ensure electrical isolation.
Regarding claim 9, Choi discloses of GGNMOS transistor structure according to claim 1 and grounded NMOS is shorten as GGNMOS. As such it would have been obvious to form a structure wherein the positive electrode is connected to an input/output end; and the negative electrode is grounded in order to form grounded NMOS (GGNMOS).
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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