DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tong et al. (CN114730776A, of record).
Regarding claim 1, Tong et al. discloses, as shown in Figure 7, a display panel (100) comprising:
an array substrate (101);
an opposed substrate (102), arranged opposite to the array substrate; and
a support column (1021,1016), disposed between the array substrate and the opposed substrate;
wherein, the array substrate comprises:
a first substrate (1011);
a thin film transistor layer (130), arranged on one side of the first substrate near the opposed substrate;
a first spacer structure (1021), arranged on one side of the thin film transistor layer near the opposed substrate;
a spacer layer (1013), arranged on the side of the first spacer structure near the opposed substrate, wherein a first opening (1015, 1017) is defined in the spacer layer and located on the side of the first spacer structure near the opposed substrate; and
a second spacer structure (1016), filled in the first opening and protrudes from a surface of the spacer layer, which is near the opposed substrate;
wherein the support column is disposed between the opposed substrate and the second spacer structure, and a depth of the first opening is less than a thickness of the spacer layer.
Regarding claim 2, Tong et al. discloses the spacer layer comprises a color resistance layer (color light filtration located on the array substrate 101, page ) located on one side of the thin film transistor layer away from the first substrate and a flat layer (1019) covering the color resistance layer, the color resistance layer comprises a plurality of color resistance blocks (a plurality of pixels (1025) , the first spacer structure and the second spacer structure are disposed between adjacent the color resistance blocks, and the first opening is defined in the flat layer.
Regarding claim 3, Tong et al. discloses the opposed substrate comprises a second substrate and a black matrix layer (not shown, page of Tong et al.) arranged on one side of the second substrate near the array substrate, the first spacer structure (1021) and the second spacer structure (1016) are orthogonally projected on the second substrate within a projection of the black matrix layer on the second substrate.
Regarding claim 4, Tong et al. discloses the support column is located on one side of the black matrix layer away from the second substrate and disposed between the black matrix layer and the second spacer structure.
Regarding claim 5, Tong et al. discloses the array substrate further comprises a light shielding layer (1110b) arranged on one side of the color resistance layer away from the thin film transistor layer, the light shielding layer comprises a plurality of first light shielding portions arranged in a first direction and extending in a second direction, and the first direction intersects with the second direction, the black matrix layer (110b) comprises a plurality of second shading portions arranged in the second direction and extending in the first direction, and a plurality of first shading portions intersect with a plurality of second shading portions to define a plurality of sub-pixel regions, a plurality of color blocking blocks are arranged within a plurality of sub-pixel regions.
Regarding claim 6, Tong et al. discloses a material of a shading layer is conductive material, or the material of the shading layer is the same as a material of the black matrix layer.
Regarding claim 7, Tong et al. discloses the thin film transistor layer comprises a plurality of data lines (1024) arranged in the first direction and extending in the second direction, and a plurality of scanning lines (gate line 1022) arranged in the second direction and extending in the first direction, and a forward projection of the data lines on the first substrate is located within a forward projection of the first shading portion on the first substrate, a forward projection of the scanning line on the first substrate is located within a forward projection of the second shading portion on the first substrate (Figure 2).
Regarding claim 14, Tong et al. discloses the spacer layer covers a portion of the first spacer structure, and an aperture of the first opening near the first spacer structure on one side is smaller than a width of the first spacer structure in a direction parallel to the first substrate, and the first opening is spaced apart from the color blocking block.
Regarding claim 15, Tong et al. discloses both a material of the first spacer structure and a material of the second spacer structure comprise organic materials.
Regarding claim 16, Tong et al. discloses, as shown in Figure 7, a display device, comprising a backlight module and a display panel disposed on an emitting light side of the backlight module, a display panel (100) comprising:
an array substrate (101);
an opposed substrate (102), arranged opposite to the array substrate; and
a support column (1021,1016), disposed between the array substrate and the opposed substrate;
wherein, the array substrate comprises:
a first substrate (1011);
a thin film transistor layer (130), arranged on one side of the first substrate near the opposed substrate;
a first spacer structure (1021), arranged on one side of the thin film transistor layer near the opposed substrate;
a spacer layer (1013), arranged on the side of the first spacer structure near the opposed substrate, wherein a first opening (1015, 1017) is defined in the spacer layer and located on the side of the first spacer structure near the opposed substrate; and
a second spacer structure (1016), filled in the first opening and protrudes from a surface of the spacer layer, which is near the opposed substrate;
wherein the support column is disposed between the opposed substrate and the second spacer structure, and a depth of the first opening is less than a thickness of the spacer layer.
Regarding claim 17, Tong et al. discloses the spacer layer comprises a color resistance layer (color light filtration located on the array substrate 101, page ) located on one side of the thin film transistor layer away from the first substrate and a flat layer (1019) covering the color resistance layer, the color resistance layer comprises a plurality of color resistance blocks (a plurality of pixels (1025) , the first spacer structure and the second spacer structure are disposed between adjacent the color resistance blocks, and the first opening is defined in the flat layer.
Regarding claim 18, Tong et al. discloses the opposed substrate comprises a second substrate and a black matrix layer (not shown, page of Tong et al.) arranged on one side of the second substrate near the array substrate, the first spacer structure (1021) and the second spacer structure (1016) are orthogonally projected on the second substrate within a projection of the black matrix layer on the second substrate.
Regarding claim 19, Tong et al. discloses the spacer layer covers a portion of the first spacer structure, and an aperture of the first opening near the first spacer structure on one side is smaller than a width of the first spacer structure in a direction parallel to the first substrate, and the first opening is spaced apart from the color blocking block (Figures).
Regarding claim 20, Tong et al. discloses a material of the first spacer structure and a material of the second spacer structure comprise organic materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (CN114730776A, of record) in view of Li et al. (CN107611145A, of record).
Regarding claim 8, Tong et al. discloses the array substrate further comprises a third spacer structure (1307) disposed between the thin film transistor layer and the spacer layer (1013), a second opening (1017) opened in the spacer layer and located on one side near the opposed substrate of the third spacer structure (1307), and a fourth spacer structure (1018), and the fourth spacer structure is filled in the second opening. Tong et al. does not disclose a surface of the fourth spacer structure near the opposed substrate side does not exceed the surface of the spacer layer near the opposed substrate side. However, Li et al. discloses a surface of the fourth spacer structure (709) near the opposed substrate side does not exceed the surface of the spacer layer (707) near the opposed substrate side. Note Figure 7 of Li et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the fourth spacer structure of Tong et al. that does not exceed the surface of the spacer layer, such as taught by Li et al. in order reduce the height of the pixel electrode.
Regarding claim 9, Tong et al. and Li et al. disclose the thin film transistor layer further comprises a plurality of thin film transistors (a plurality of pixels, and thin film transistors are present for each pixel cell, 120, 130) arranged on the first substrate and corresponding to a plurality of sub-pixel regions, the thin film transistors comprises a first thin film transistor, the first thin film transistor comprises a first active layer, a first gate, and a first source and a first drain respectively connected to both sides of the first active layer, and one end of the first drain is connected to the first active layer, and the other end extends to the surface of the first spacer structure on one side away from the first substrate.
Regarding claim 10, Tong et al. and Li et al. disclose the thin film transistors further comprises a second thin film transistor (120, 130), the second thin film transistor comprises a second active layer, a third gate, and a second source and a second drain respectively connected to both sides of the second active layer, and one end of the second drain is connected to the second active layer, and the other end extends to the surface of the third spacer structure on one side away from the first substrate.
Regarding claim 11, Tong et al. and Li et al. disclose the array substrate further comprises a first electrode layer (no label, above 100, Figure 7) located on the side of the spacer layer far from the thin film transistor layer, the first electrode layer comprises a first electrode (no label, above 100, on the left, Figure 7) connected to the first thin film transistor and a second electrode (no label, above 100, one the right, Figure 7) connected to the second thin film transistor, each of the sub-pixel regions comprises a first sub-pixel region corresponding to the first thin film transistor, and a second sub-pixel region corresponding to the second thin film transistor; one end of the first electrode (1310, Figure 7) extends into the first opening and is connected to the first drain electrode, the other end extends into the first sub-pixel region, and the second spacer structure is located on the side of the first electrode away from the first substrate; and one end of the second electrode extends into the second opening and is connected to the second drain electrode, while the other end extends into the second sub-pixel region, and the fourth spacer structure is located on the side of the second electrode away from the first substrate.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (CN114730776A, of record) in view of Li et al. (CN107611145A, of record) and further in view of Kim et al. (US 2009/0231522).
Regarding claim 12, Tong et al. and Li et al. disclose the claimed invention including the display panel as explained in the above rejection. Tong et al. and Li et al. do not disclose a color of the color blocking block in the first sub-pixel region is blue, and the color of the color blocking block in the second sub-pixel region is red or green. However, Kim et al. discloses a display panel having a color of the color blocking block in the first sub-pixel region is blue (B1-B3), and the color of the color blocking block in the second sub-pixel region is red (R1-R3) or green (G1-G3). Note Figures 1-3 and [0054] of Kim et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the color blocking block of Tong et al. and Li et al. having colors as claimed, such as taught by Kim et al. in order to have the desired colors.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (CN114730776A, of record) in view of Li et al. (CN107611145A, of record) and further in view of Park (KR-20060099886-A).
Tong et al. and Li et al. disclose the claimed invention including the display panel as explained in the above rejection. Tong et al. and Li et al. disclose the array substrate further comprises: a second electrode layer, is arranged on the side of the first electrode layer far from the spacer layer; an insulation layer, is arranged on the side of the second electrode layer away from the first electrode layer; a third electrode layer, is arranged on the side of the insulation layer away from the second electrode layer; wherein, the first electrode layer is connected to the second electrode layer. Tong et al. and Li et al. do not disclose forms a storage capacitor structure. However, Park discloses the display having a storage capacitor structure comprising the second electrode (190) and the third electrode layer (270). Note Figures 6 and 12 of Park. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the display of Tong et al. and Li et al. having a capacitor, such as taught by Park in order to form a complete basis unit of pixel.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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