DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1 lines 20-21, “a predetermined range” ---, should be corrected to ---, “the predetermined range” ---.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al (US Patent No. 6958895) in view of Paice et al (US Patent No. 4618906).
Regarding claim 1, Radosavljevic discloses a switching arrangement (i.e., SA; see for example fig. 6 as shown below, Col. 10 lines 11+), comprising: a switching device (S3, S4), a magnetic drive (52); and a control circuit (10), wherein the control circuit (10) comprises: a current sensing unit (100, 104) configured to measure a load current (IL) flowing through the switching device (S3, S4), a trigger level detector (i.e., 50, 50'; Latch mechanism 80 may be toggled to the tripped position by the fault detection circuitry, as described above, or by a user accessible test button 50. Alternatively, latch mechanism 80 may be tripped by the fault detection circuitry, as described above, and by an electrical test button 50'. The electrical test button 50' produces a simulated condition configured to test a portion of, or all of, the detection circuitry. A test acceptance signal toggles latch mechanism 80 to the tripped position. The simulated condition may be a test signal or an induced fault signal. Hereinafter, both of these signals will be referred to as simulated fault conditions; see for example Col. lines 11+) having an input (B) coupled to an output (i.e., C; the power feed B of 50 and 50' is clamped to the output node C of the current sensor-detector 100-104 via R25) of the current sensing unit (100, 104), a reset circuit (i.e., 60; The reset mechanism includes reset button 60, contacts 62, and reset solenoid 64. When reset button 60 is depressed, contacts 62 are closed to thereby initiate a test procedure. If the test procedure is successful, reset solenoid 64 is actuated, and latch mechanism 80 is toggled to reset device 10. When device 10 has an internal fault condition, the test procedure is unsuccessful, and the circuitry does not transmit a reset signal. The reset solenoid 64 is not actuated, and the device is not reset. As described above, latch mechanism 80 is toggled between the tripped state and the reset state by trip solenoid 52 and reset solenoid 64, respectively; see for example Col. lines 11+) having an input (D) coupled to an output (i.e., E; the output of 50/50' is reflected to node E via trip indicator 130) of the trigger level detector (i.e., 50, 50'; Latch mechanism 80 may be toggled to the tripped position by the fault detection circuitry, as described above, or by a user accessible test button 50. Alternatively, latch mechanism 80 may be tripped by the fault detection circuitry, as described above, and by an electrical test button 50'. The electrical test button 50' produces a simulated condition configured to test a portion of, or all of, the detection circuitry. A test acceptance signal toggles latch mechanism 80 to the tripped position. The simulated condition may be a test signal or an induced fault signal. Hereinafter, both of these signals will be referred to as simulated fault conditions; see for example Col. lines 11+); and a driver (Ql, Q2) having a control input (F/RlO, L/R16), wherein a terminal (G) of the driver (Ql, Q2) is coupled to a first terminal (H) of the magnetic drive (52), wherein that the switching device (S3, S4) comprises a contact bridge (80), wherein the magnetic drive (52) is coupled to the contact bridge (80), and wherein the control circuit (10) comprises a timer (140) having a reset input (I) coupled to an output (i.e., K, M; the gate F/RlO of Ql is clamped to the timer CKT 140 node M via C7, and the gate L/R16 of Q2 is clamped to the timer CKT 140 node K via R16) of the reset circuit (i.e., 60; The reset mechanism includes reset button 60, contacts 62, and reset solenoid 64. When reset button 60 is depressed, contacts 62 are closed to thereby initiate a test procedure. If the test procedure is successful, reset solenoid 64 is actuated, and latch mechanism 80 is toggled to reset device 10. When device 10 has an internal fault condition, the test procedure is unsuccessful, and the circuitry does not transmit a reset signal. The reset solenoid 64 is not actuated, and the device is not reset. As described above, latch mechanism 80 is toggled between the tripped state and the reset state by trip solenoid 52 and reset solenoid 64, respectively; see for example Col. lines 11+), and wherein a [the] control input (F/RlO, L/R16) of the driver (Ql, Q2) is coupled to an output (i.e., K, M; the gate F/RlO of Ql is clamped to the timer CKT 140 node M via C7, and the gate L/R16 of Q2 is clamped to the timer CKT 140 node K via R16) of the timer (140).
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Radosavljevic does not explicitly disclose wherein the trigger level detector is configured to detect whether a signal at the input of the trigger level detector is in a predetermined range, which indicates that the load current is over a predetermined limit, and based on detecting that the signal at the input of the trigger level detector is in a predetermined range, setting the switching device in a switched-off-state.
Paice discloses a hybrid solid state/mechanical switch (i.e., see for example fig. 1, Col. 2 lines 20+); wherein the trigger level detector (i.e., such as trigger level detector 40 detects the leakage current in the solid state switching device that potentially caused by any overload event; for instance, switch failure protection is provided by circuitry which detects leakage current in the solid state switching device and additional circuitry which detects a short circuit in the solid state switching device or a malfunction of the mechanical contacts. To detect leakage current in the solid-state switching device, a diode 36 is placed in series with GTO 18 and a resistor 38 is connected in parallel with the diode. The voltage across this parallel circuit is then delivered to a threshold detector 40 which produces a logic output signal when the voltage across the parallel circuit exceeds a predetermined magnitude. This leakage current logic signal is delivered by line 42 to logic gate 44 which is used to prevent a false leakage current indication during turn-on and turn-off of the switch. This function is performed with the aid of an input signal on line 46 from the control logic circuit 30 which blocks the threshold detector output logic signal during turn-on and turn-off of the switch. At other times, when leakage current is detected, a logic signal is passed to crowbar firing circuit 48, thereby turning on thyristor 22 to cause current flow which is sufficient to blow the fuse 12; see for example fig. 1, Col. 2 lines 20+) is configured to detect (i.e., such as detector 40 is configured to detect the leakage current in the solid state switching device that potentially caused by any overload event; see for example fig. 1, Col. 2 lines 20+) whether a signal (i.e., such as signal of the leakage current in the solid state switching device that potentially caused by any overload event; see for example fig. 1, Col. 2 lines 20+) at the input (i.e., such as input terminal to detector 40 coming from circuit diode 36 and resistor 38; see for example fig. 1, Col. 2 lines 20+) of the trigger level detector (i.e., such as trigger level detector 40 detects the leakage current in the solid state switching device that potentially caused by any overload event; for instance, switch failure protection is provided by circuitry which detects leakage current in the solid state switching device and additional circuitry which detects a short circuit in the solid state switching device or a malfunction of the mechanical contacts. To detect leakage current in the solid-state switching device, a diode 36 is placed in series with GTO 18 and a resistor 38 is connected in parallel with the diode. The voltage across this parallel circuit is then delivered to a threshold detector 40 which produces a logic output signal when the voltage across the parallel circuit exceeds a predetermined magnitude. This leakage current logic signal is delivered by line 42 to logic gate 44 which is used to prevent a false leakage current indication during turn-on and turn-off of the switch. This function is performed with the aid of an input signal on line 46 from the control logic circuit 30 which blocks the threshold detector output logic signal during turn-on and turn-off of the switch. At other times, when leakage current is detected, a logic signal is passed to crowbar firing circuit 48, thereby turning on thyristor 22 to cause current flow which is sufficient to blow the fuse 12; see for example fig. 1, Col. 2 lines 20+) is in a predetermined range (i.e., such as in predetermined range that is set by the current sensor 56; for instance, from the waveforms of FIG. 2, it is clear that current flows through GTO 18 under normal conditions between times T.sub.1 and T.sub.3 and between times T.sub.6 and T.sub.7. Therefore, for these time intervals, logic gate 44 blocks the output of threshold detector 40. At all other times, any output from threshold detector 40 will trigger crowbar firing circuit 48 thereby blowing fuse 12. To operate the short circuit protection circuitry, delay circuit 60 inhibits a logic turn-off signal from passing to line 62 for the time period between times T.sub.5 and T.sub.8. At time T.sub.8, the signal would appear on line 62. If at this time, current sensor 56 indicates on line 58 that current continues to flow through the switch, crowbar firing circuit 48 would again be triggered to turn on thyristor 22; see for example fig. 2, Col. 2 lines 20+), which indicates that the load current (i.e., such as the load current at power line 16; see for example fig. 1, Col. 2 lines 20+) is over a predetermined limit (i.e., such as over predetermined limit; for instance, the voltage across this parallel circuit is then delivered to a threshold detector 40 which produces a logic output signal when the voltage across the parallel circuit exceeds a predetermined magnitude. This leakage current logic signal is delivered by line 42 to logic gate 44 which is used to prevent a false leakage current indication during turn-on and turn-off of the switch; see for example fig. 1, Col. 2 lines 20+), and based on detecting (i.e., such as detector 40 is configured to detect the leakage current in the solid state switching device that potentially caused by any overload event; see for example fig. 1, Col. 2 lines 20+) that the signal (i.e., such as signal of the leakage current in the solid state switching device that potentially caused by any overload event; see for example fig. 1, Col. 2 lines 20+) at the input (i.e., such as input terminal to detector 40 coming from circuit diode 36 and resistor 38; see for example fig. 1, Col. 2 lines 20+) of the trigger level detector (i.e., such as trigger level detector 40 detects the leakage current in the solid state switching device that potentially caused by any overload event; for instance, switch failure protection is provided by circuitry which detects leakage current in the solid state switching device and additional circuitry which detects a short circuit in the solid state switching device or a malfunction of the mechanical contacts. To detect leakage current in the solid-state switching device, a diode 36 is placed in series with GTO 18 and a resistor 38 is connected in parallel with the diode. The voltage across this parallel circuit is then delivered to a threshold detector 40 which produces a logic output signal when the voltage across the parallel circuit exceeds a predetermined magnitude. This leakage current logic signal is delivered by line 42 to logic gate 44 which is used to prevent a false leakage current indication during turn-on and turn-off of the switch. This function is performed with the aid of an input signal on line 46 from the control logic circuit 30 which blocks the threshold detector output logic signal during turn-on and turn-off of the switch. At other times, when leakage current is detected, a logic signal is passed to crowbar firing circuit 48, thereby turning on thyristor 22 to cause current flow which is sufficient to blow the fuse 12; see for example fig. 1, Col. 2 lines 20+) is in a predetermined range (i.e., such as in predetermined range that is set by the current sensor 56; for instance, from the waveforms of FIG. 2, it is clear that current flows through GTO 18 under normal conditions between times T.sub.1 and T.sub.3 and between times T.sub.6 and T.sub.7. Therefore, for these time intervals, logic gate 44 blocks the output of threshold detector 40. At all other times, any output from threshold detector 40 will trigger crowbar firing circuit 48 thereby blowing fuse 12. To operate the short circuit protection circuitry, delay circuit 60 inhibits a logic turn-off signal from passing to line 62 for the time period between times T.sub.5 and T.sub.8. At time T.sub.8, the signal would appear on line 62. If at this time, current sensor 56 indicates on line 58 that current continues to flow through the switch, crowbar firing circuit 48 would again be triggered to turn on thyristor 22; see for example fig. 2, Col. 2 lines 20+), setting the switching device (i.e., such as solid-state switching device 18; for instance, FIG. 2 is a series of waveforms which illustrate the operation of the circuit of FIG. 1. In FIG. 2, waveform 70 represents the gate current in solid state switching device 18, waveform 72 represents current in the main conduction path of solid-state switching device 18, waveform 74 represents a command signal delivered by control logic circuit to contact operating mechanism 34, waveform 76 represents the current through mechanical contacts 10, and waveform 78 represents the total current through the hybrid switch. At time T.sub.1, GTO firing circuit 32 delivers a gate pulse to GTO 18 thereby causing conduction through its main current conducting path. Once the solid-state switching device is conducting current, a command signal is delivered to the contact operating mechanism 34 at time T.sub.2. At time T.sub.3, current begins to flow through the mechanical contacts. Because of the low voltage drop of the mechanical contacts, current stops flowing through GTO 18; see for example fig. 1, Col. 2 lines 20+) in a switched-off-state (i.e., such as switched-off-state; for instance, To turn off the hybrid switch, at time T.sub.4, gate current is again applied to GTO 18 and at a later time T.sub.5, a contact opening command signal is provided to contact operating mechanism 34. At time T.sub.6, the mechanical contacts open and current is shunted through GTO 18. At time T.sub.7, a turn-off gate signal is applied to GTO 18. From the waveforms of FIG. 2, it is clear that current flows through GTO 18 under normal conditions between times T.sub.1 and T.sub.3 and between times T.sub.6 and T.sub.7. Therefore, for these time intervals, logic gate 44 blocks the output of threshold detector 40. At all other times, any output from threshold detector 40 will trigger crowbar firing circuit 48 thereby blowing fuse 12. To operate the short circuit protection circuitry, delay circuit 60 inhibits a logic turn-off signal from passing to line 62 for the time period between times T.sub.5 and T.sub.8. At time T.sub.8, the signal would appear on line 62. If at this time, current sensor 56 indicates on line 58 that current continues to flow through the switch, crowbar firing circuit 48 would again be triggered to turn on thyristor 22; see for example fig. 1, Col. 2 lines 20+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the trigger detector device in Radosavljevic, as taught by Paice, as it provides the advantage of optimizing the circuit design towards efficiency, reliability and safety.
Regarding claim 3, Radosavljevic in view of Paice and the teachings of Radosavljevic as modified by Paice have been discussed above.
Radosavljevic further discloses the switching arrangement (i.e., SA; see for example fig. 6 as shown above, Col. 10 lines 11+), wherein the control circuit (10) comprises a first input (200) which is coupled to an input (i.e., terminal 200 is clamped to 140 via Rl as to charge ClO in 140; such as the timing circuit 140 includes: diode D2; resistors R15, R12, and Rll; capacitor ClO and transistor Q3. When the reset button 60 is depressed, ClO begins charging through D2 and R15 while the simulated fault signal through Rl is being introduced. ClO is charged to a voltage that turns transistor Q3 ON after a predetermined interval, typically one and a half line cycles (25 milliseconds); see for example Col. 10 lines 11+) of the timer (140).
Regarding claim 10, Radosavljevic in view of Paice and the teachings of Radosavljevic as modified by Paice have been discussed above.
Radosavljevic further discloses the switching arrangement (i.e., SA; see for example fig. 6 as shown above, Col. 10 lines 11+), a method (i.e., SA; see for example fig. 6 as shown above, Col. 10 lines 11+) for operating a switching arrangement (i.e., SA; see for example fig. 6 as shown above, Col. 10 lines 11+), comprising: measuring a load current (IL) that flows through a switching device (S3, S4) by a current sensing unit (100, 104); generating a trigger signal (i.e., such as the user can trigger the signal manually by pressing button 50, and/or the electronic simulator 50' may trigger the signal electrically by closing switch S2), by a trigger level detector (i.e., 50, 50'; Latch mechanism 80 may be toggled to the tripped position by the fault detection circuitry, as described above, or by a user accessible test button 50. Alternatively, latch mechanism 80 may be tripped by the fault detection circuitry, as described above, and by an electrical test button 50'. The electrical test button 50' produces a simulated condition configured to test a portion of, or all of, the detection circuitry. A test acceptance signal toggles latch mechanism 80 to the tripped position. The simulated condition may be a test signal or an induced fault signal. Hereinafter, both of these signals will be referred to as simulated fault conditions; see for example Col. lines 11+) as a function (i.e., voltage signal versus time) the of a signal (i.e., the trip/test signal) provided by the current sensing unit (100, 104); generating a reset signal (i.e., the signal is generated when pressing/depressing button 60) by a reset circuit (i.e., 60; The reset mechanism includes reset button 60, contacts 62, and reset solenoid 64. When reset button 60 is depressed, contacts 62 are closed to thereby initiate a test procedure. If the test procedure is successful, reset solenoid 64 is actuated, and latch mechanism 80 is toggled to reset device 10. When device 10 has an internal fault condition, the test procedure is unsuccessful, and the circuitry does not transmit a reset signal. The reset solenoid 64 is not actuated, and the device is not reset. As described above, latch mechanism 80 is toggled between the tripped state and the reset state by trip solenoid 52 and reset solenoid 64, respectively; see for example Col. lines 11 +) as a function (i.e., voltage signal versus time) of the trigger signal (i.e., such as the user can trigger the signal manually by pressing button 50, and/or the electronic simulator 50' may trigger the signal electrically by closing switch S2); providing the reset signal (i.e., such as the user can trigger the signal manually by pressing button 50, and/or the electronic simulator 50' may trigger the signal electrically by closing switch S2) to a reset input (I) of a timer (140); and stopping a pulse (i.e., such as a pulse/signal of the timing circuit 140; see for example Col. 10 lines 56+) of a timer signal (i.e., such as a pulse/signal of the timing circuit 140; see for example Col. 10 lines 56+) which is generated by the timer (140) and is provided to a driver (Ql, Q2) at the point of time (i.e., such as the time setting; see for example Col. 10 lines 56+ ), when the trigger signal (i.e., such as the user can trigger the signal manually by pressing button 50, and/or the electronic simulator 50' may trigger the signal electrically by closing switch S2) or the signal (i.e., the test/trip signal) derived from the trigger signal (i.e., such as the user can trigger the signal manually by pressing button 50, and/or the electronic simulator 50' may trigger the signal electrically by closing switch S2) is provided to the reset input (I) of the timer (140), wherein the driver (Ql, Q2) is coupled to a magnetic drive (52) and the magnetic drive (52) is coupled to a contact bridge (80) of the switching device (S3, S4).
Also, Paice furthermore discloses the hybrid solid state/mechanical switch (i.e., see for example fig. 1, Col. 2 lines 20+); generating a trigger signal (i.e., such as generating trigger signal line 42; see for example fig. 1, Col. 2 lines 20+) by a trigger level detector (i.e., such as trigger level detector 40; see for example fig. 1, Col. 2 lines 20+) as a function (i.e., such as function of logic signals Zero and One; see for example fig. 1, Col. 2 lines 20+) of a signal (i.e., such as signal at node 26 coming from current sensor 56; see for example fig. 1, Col. 2 lines 20+) provided by the current sensing unit (i.e., such as current sensing unit 56; see for example fig. 1, Col. 2 lines 20+); generating a reset signal (i.e., such as generating reset signals 50, 52, 54; see for example fig. 1, Col. 2 lines 20+) by a reset circuit (i.e., such as reset circuit 30, 66) as a function (i.e., such as function of logic signals Zero and One; see for example fig. 1, Col. 2 lines 20+) of the trigger signal (i.e., such as generating trigger signal line 42; see for example fig. 1, Col. 2 lines 20+); providing the reset signal (i.e., such as generating reset signals 50, 52, 54; see for example fig. 1, Col. 2 lines 20+) to a reset input (i.e., such as reset input line 52; see for example fig. 1, Col. 2 lines 20+) of a timer (i.e., such as timer 60; see for example fig. 1, Col. 2 lines 20+); stopping a pulse (i.e., such as pulse wave; see for example fig. 1, Col. 2 lines 20+) of a timer signal (i.e., such as timer signal line 62; see for example fig. 1, Col. 2 lines 20+) which is generated by the timer (i.e., such as timer 60; see for example fig. 1, Col. 2 lines 20+) and is provided to a driver (i.e., such as via AND logic gate 66 to driver 48 in order to drive thyristor 22; see for example fig. 1, Col. 2 lines 20+) at the point of time (i.e., such as point of time; see for example the timing sequence in fig. 2, Col. 2 lines 20+).
And, as for the rest of the limitations/features in claim 10 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Claims 4-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al (US Patent No. 6958895) in view of Paice et al (US Patent No. 4618906) and further in view of Oshita et al (US Publication No. 20200083009).
Regarding claim 4, Radosavljevic in view of Paice and the teachings of Radosavljevic as modified by Paice have been discussed above.
Radosavljevic further discloses the switching arrangement (i.e., SA; see for example fig. 6 as shown above, Col. 10 lines 11+).
Paice furthermore discloses the hybrid solid state/mechanical switch (i.e., see for example fig. 1, Col. 2 lines 20+).
Neither Radosavljevic nor Paice explicitly discloses wherein the timer is configured: to start a pulse of a timer signal provided at the output of the timer when receiving an edge of a pulse at the input of the timer; and to end the pulse of the timer signal when receiving an edge of a pulse at the reset input of the timer or after a predetermined time.
Oshita discloses a pulse control device (i.e., 10; see for example fig. 8 as shown below, para. [0115]- [0138]); wherein the timer (250) is configured: to start a pulse (i.e., such as a pulse; see for example para. [0053]) of a timer signal (i.e., such as a timer signal; see for example para. [0116]) provided at the output (N) of the timer (250) when receiving an edge of a pulse (i.e., such as an edge of a pulse, at a rising edge in it; see for example [0094]) at the input (0) of the timer (250); and to end the pulse (i.e., such as a pulse; see for example para. [0053]) of the timer signal (i.e., such as a timer signal; see for example para. [0116]) when receiving an edge of a pulse (i.e., such as an edge of a pulse, at a rising edge in it; see for example para. [0094]) at the reset input (i.e., such as to low level (=GND) according to the reset signal S2 (for example, at a rising edge in it), which is fed to the reset terminal of the D flip-flop 241; see for example fig. 6, para. [0094]) of the timer (250) or after a predetermined time (i.e., such as a predetermined time; see for example the timing chart in fig. 7, para. [0100]).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the time-setting scheme in Radosavljevic, as taught by Oshita, as it provides the advantage of optimizing the circuit design towards adding precise time delays to electrical circuits, enabling automated, and enhancing safety.
Regarding claim 5, Radosavljevic in view of Paice and further in view of Oshita and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita have been discussed above as well.
Oshita further discloses the pulse control device (i.e., 10; see for example fig. 8 as shown above, para. [0115]- [0138]); wherein the control circuit (10) comprises a de-energizing unit (110) that is coupled to a second terminal (T21) of the magnetic drive (21); and wherein the output (52) of the trigger level detector (230) is coupled via the reset circuit (240) to a control input (Gl) of the de-energizing unit (110).
Regarding claim 6, Radosavljevic in view of Paice and further in view of Oshita and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita have been discussed above as well.
Oshita further discloses the pulse control device (i.e., 10; see for example fig. 8 as shown above, para. [0115]- [0138]); wherein the driver (120) is configured to control a first current (Ix) that flows through the first terminal (T22) of the magnetic drive (21), wherein the de energizing unit (110) is configured to control a second current (ly) that flows through the second terminal (T21) of the magnetic drive (21), and wherein the first current (Ix) and the second current (ly) set an armature (i.e., such as the armature 21c; see for example fig. 3, para. [0058]) of the switching device (22) in a switched-off position (i.e., such as a switched off position OPEN/OFF; that is, the off-state of the mechanical relay 20; see for example para. [0060]) when the trigger level detector (230) provides a pulse (i.e., such as a pulse; see for example para. [0053]) at the output (52) of the trigger level detector (230).
Regarding claim 7, Radosavljevic in view of Paice and further in view of Oshita and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita have been discussed above as well.
Oshita further discloses the pulse control device (i.e., 10; see for example fig. 8 as shown above, para. [0115]- [0138]); wherein the control circuit (10) comprises a further trigger level detector (220) having an input (Vref) coupled to a first input (EN) of the control circuit (10) and wherein an output (51) of the further trigger level detector (220) is coupled to the control input (Gl) of the de- energizing unit (110).
Regarding claim 8, Radosavljevic in view of Paice and further in view of Oshita and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita have been discussed above as well.
Oshita further discloses the pulse control device (i.e., 10; see for example fig. 8 as shown above, para. [0115]- [0138]); wherein the further trigger level detector (220) is configured to determine (i.e., such as to determine by comparing the feedback voltage Vfb, which is fed to the inverting input terminal (-) of the comparator 220, with a reference voltage Vref; see for example para. [0072]) whether a signal (i.e., such as a signal; see for example para. [0072]) at the input (Vfb, Vref) of the further trigger level detector (220) is in a further predetermined range (i.e., such as a further predetermined range and that is between the low level (=GND) and the high level (=Vreg); see for example para. [0072]).
Regarding claim 9, Radosavljevic in view of Paice and further in view of Oshita and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita have been discussed above as well.
Oshita further discloses the pulse control device (i.e., 10; see for example fig. 8 as shown above, para. [0115]- [0138]); wherein the reset circuit (240) is configured to provide a further reset signal (53) with a pulse (i.e., such as a pulse; see for example para. [0073]) having a predetermined duration (i.e., such as a predetermined duration; see for example para. [0073]) to the control input (Gl) of the de-energizing unit (110).
Regarding claim 11, Radosavljevic in view of Paice and further in view of Oshita and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita have been discussed above as well.
Oshita further discloses the pulse control device (i.e., 10; see for example fig. 8 as shown above, para. [0115]- [0138]); wherein the method (i.e., 10; see for example fig. 8 as shown above, para. [0115]- [0138]) further comprises: generating a further reset signal (53) with a pulse (i.e., such as a pulse; see for example para. [0073]) having a predetermined duration (i.e., such as a predetermined duration; see for example para. [0073]) as a function of the trigger signal (i.e., voltage signal S3 versus time) by the reset circuit (240); and providing the further reset signal (53) to a de-energizing unit (110) which is coupled to the magnetic drive (21).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Radosavljevic et al (US Patent No. 6958895) in view of Paice et al (US Patent No. 4618906) and in view of Oshita et al (US Publication No. 20200083009) and further in view of Gaspari et al (US Patent No. 4150369).
Regarding claim 12, Radosavljevic in view of Paice and further in view of Oshita and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita have been discussed above as well.
Radosavljevic discloses the switching arrangement (i.e., SA; see for example fig. 6 as shown above, Col. 10 lines 11+).
Paice further discloses the hybrid solid state/mechanical switch (i.e., see for example fig. 1, Col. 2 lines 20+).
Oshita furthermore discloses the pulse control device (i.e., 10; see for example fig. 8 as shown below, para. [0115]- [0138]).
Neither Radosavljevic nor Paice nor Oshita explicitly discloses wherein the control circuit further comprises an emergency input, and wherein the emergency input is coupled to the magnetic drive via the de-energizing unit.
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Gaspari discloses an intrusion alarm system (i.e., P; see for example fig. 1 as shown below, Col. 3 lines 54+); wherein the control circuit (P) further comprises an emergency input (Q), and wherein the emergency input (Q) is coupled to the magnetic drive (30) via the de-energizing unit (48).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the emergency-input in Radosavljevic, as taught by Gaspari, as it provides the advantage of optimizing the circuit design towards improving personnel safety and equipment protection.
Regarding claim 13, Radosavljevic in view of Paice and in view of Oshita and further in view of Gaspari and the teachings of Radosavljevic as modified by Paice have been discussed above. Also, the teachings of Radosavljevic as modified by Oshita and the teachings of Radosavljevic as modified by Gaspari have been discussed above as well.
Gaspari further discloses the intrusion alarm system (i.e., P; see for example fig. 1 as shown above, Col. 3 lines 54+); wherein the emergency input (Q) is coupled to a control input (R) of the de-energizing unit (48) via a surge protection unit (12) and an emergency trigger level detector (46).
Claim 2 is cancelled.
Conclusion
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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