Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: OSR-903-SW
Filling Date: 12/06/23
Priority Date: 6/18/21
Inventor: Pfeuffer
Examiner: Bilkis Jahan
DETAILED ACTION
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claims 25, 30-31, 33, 37, 42 and 43 are objected to because of the following informalities:
Claims 25, 30-31, 33, 37, 42 and 43 are recited “metallization”. However, it should be “metallization”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 in line 4 and claim 26 in line 2 recites “optionally”. However, this is not a definite language.
Claim 37 in line 4 recite “optionally”. However, this is not a definite language.
Claims 38-44 are dependent from claim 37. Therefore, claims 38-44 are also rejected under 112 2nd rejection.
Inasmuch as understood in light of 112 2nd rejection and claims objection, the art rejections as follows:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 25-34 and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yahara et al (US 2009/0039374 A1).
Regarding claim 25, Yahata discloses an optoelectronic semiconductor chip (Fig. 2) comprising: a semiconductor body 11-13 (Para. 37) comprising: an n-doped region 11; a p-doped region 13 optionally comprising a p-type current distribution layer; and an active region 12 arranged between the n-doped region 11 and the p-doped region 13; a first dielectric layer 17 (bottom horizontal portion, Para. 44) arranged on the p-doped region 13; a mirror layer 18 (Para. 41) comprising a metal and arranged on the first dielectric layer 17 (bottom portion), wherein the first dielectric layer 17 electrically insulates the mirror layer 18 from the p-doped region 13 and the n- doped region 11; a second dielectric layer 17 (top horizontal portion) arranged on the mirror layer 18; a metallisation layer 19 (Para. 42) arranged on the second dielectric layer 17 (top portion), wherein the metallisation layer 19 is electrically isolated from the mirror layer 18 and electrically contacts the p-doped region 13; and an n-type contact layer 14 (Para. 38) deposited on the n-doped region 11 opposite the p-doped region 13.
Regarding claim 26, Yahata discloses the optoelectronic semiconductor chip according to claim 25, wherein at least the p-doped region 13 and the active region 12 form a first mesa structure (portion underneath 17, 18 block in left) and optionally at least a portion of the n-doped region 11 forms a second mesa structure (underneath element 14), and wherein the second mesa structure (underneath element 14) laterally protrudes the first mesa structure (portion underneath 17, 18 block in left).
Regarding claim 27, Yahata discloses the optoelectronic semiconductor chip according to claim 26, wherein the first dielectric layer 17 is arranged on a side surface of the semiconductor body 11, 12, 13 and follows a side surface of the first mesa structure (portion underneath 17, 18 block in left).
Regarding claim 28, Yahata discloses the optoelectronic semiconductor chip according to claim 27, wherein the mirror layer 18 is arranged on the first dielectric layer 17 on the side surface of the semiconductor body 11, 12, 13.
Regarding claim 29, Yahata discloses the optoelectronic semiconductor chip according to claim 26, wherein the second dielectric layer 17 follows a side surface of the semiconductor body 11, 12, 13 and follows a side surface of the first mesa structure (portion underneath 17, 18 block in left).
Regarding claim 30, Yahata discloses the optoelectronic semiconductor chip according to claim 25, wherein the optoelectronic semiconductor chip 11, 12, 13 is electrically connectable on two opposing sides (left and right) of the semiconductor chip by the metallisation layer 19 and the n-type contact layer 14.
Regarding claim 31, Yahata discloses the optoelectronic semiconductor chip according to claim 25, wherein the metallisation layer 19 comprises a contact via 16a (Para. 40) at least through the first and second dielectric layers 17 (top and bottom horizontal lines).
Regarding claim 32, Yahata discloses the optoelectronic semiconductor chip according to claim 31, wherein the contact via 16a is located centrally with regard to the semiconductor body or is located on an edge of the semiconductor body 11, 12, 13.
Regarding claim 33, Yahata discloses the optoelectronic semiconductor chip according to claim 25, wherein the metallisation layer 19 is reflective or comprises a reflective coating 16 (Para. 39, Al is reflective).
Regarding claim 34, Yahata discloses the optoelectronic semiconductor chip according to claim 25, wherein, when viewed on the mirror layer 18, the mirror layer 18 comprises at least one of a rectangular, polygonal or circular shape with an opening arranged in the center of the semiconductor body 11, 12, 13, or a rectangular, polygonal or circular shape with a recess on an edge of the mirror layer 18.
Regarding claim 36, Yahata discloses the optoelectronic semiconductor chip according to claim 25, wherein the n-type contact layer 14 comprises an at least partially transparent material (another electrode 15 is comprises ITO. So, ITO is obvious for the junction electrode 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Yahara et al (US 2009/0039374 A1) in view of Denbaars et al (US 2007/0018183 A1).
Regarding claim 35, Yahata discloses the optoelectronic semiconductor chip according to claim 25, wherein the n- doped region 11.
Yahara does not explicitly disclose the n- doped region comprises an n-type current distribution layer.
However, Denbaars discloses the n- doped region comprises an n-type current distribution layer (Para. 41). Denbaars teaches the above modification is used to obtain active layer efficiency of the device (Para. 41). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Yahata structure with Denbaars current distribution layer as suggested above to obtain active layer efficiency of the device (Para. 41).
Remark
6. The claims 37-43 and 44 will be allowed after 112 second rejection and objection will overcome.
Allowable Subject Matter
7. Claims 37-43 and 44 are allowed.
8. The following is an examiner’s statement of reasons for allowance:
9. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed method for manufacturing an optoelectronic semiconductor chip, the method comprising: depositing a release layer on the metallisation layer, wherein depositing the release layer comprises generating a through hole through the release layer in an area of the release layer, and wherein the release layer is in direct contact with the first dielectric layer and/or the second dielectric layer; gluing or solder bonding the release layer on a carrier such that the through hole is filled with a gluing material or a solder material; depositing an n-type contact layer on the n-doped region opposite the p-doped region; and removing the release layer in combination with all other limitations as recited in claim 1.
10. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817