Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (JP 2014229767 A, see attached machine translation for paragraph citations) in view of Shimizu et al. (US Patent Pub 20180204916 A1).
Regarding Claim 1, Suzuki teaches a semiconductor device comprising:
a first nitride semiconductor layer (Fig. 1, first nitride semiconductor layer 3. Paragraph 0041 (see attached machine translation) teaches 3 is formed of a nitride semiconductor material);
a second nitride semiconductor layer provided above the first nitride semiconductor layer and forming a two-dimensional electron gas between the first nitride semiconductor layer and thereof (Fig. 1, second nitride semiconductor layer 4 provided above the first nitride semiconductor layer 3. Paragraph 0047 teaches 4 is formed of a nitride semiconductor material. Paragraph 0039 teaches a two-dimensional electron gas is formed between 3 and 4);
a source electrode provided above the second nitride semiconductor layer and electrically connected to the two-dimensional electron gas (Fig. 1, source electrode 6 provided above the second nitride semiconductor layer 4 and electrically connected to the two-dimensional electron gas (see paragraph 0054). Further, paragraph 0070 teaches that the source and drain formed of a continuous metal film that first deposited and selectively etched to leave behind two portions, which are the source and drain. Therefore, since they are fabricated at the same time and of the same material, their labels are interchangeable);
a drain electrode provided above the second nitride semiconductor layer and electrically connected to the two-dimensional electron gas (Fig. 1, drain electrode 5 provided above the second nitride semiconductor layer 4 and electrically connected to the two-dimensional electron gas (see paragraph 0054);
a gate electrode provided above the second nitride semiconductor layer and arranged between the source electrode and the drain electrode (Fig. 1, gate electrode 7 provided above the second nitride semiconductor layer 4 and arranged between the source electrode 6 and the drain electrode 5);
a protective film provided above the second nitride semiconductor layer and arranged between the gate electrode and the drain electrode (Fig. 1, protective film 9s provided above the second nitride semiconductor layer 4 and arranged between the gate electrode 7 and the drain electrode 5. Paragraph 0059 teaches 9s is a protective film);
and a first oxide layer provided above the second nitride semiconductor layer and arranged only between the source electrode and a side of the gate electrode closest to the source electrode (Fig. 1, first oxide layer 8 arranged only between the source electrode 6 and a side of the gate electrode 7 closest to 6. Paragraph 0079 teaches 8 can be formed of Hafnium oxide).
Suzuki fails to teach a second oxide layer provided above the first oxide layer, wherein, at a junction interface between the first oxide layer and the second oxide layer, an oxygen area density of the first oxide layer is lower than an oxygen area density of the second oxide layer.
However, Shimizu teaches a HEMT semiconductor device having second oxide layer provided above the first oxide layer (Shimizu, fig., 1 and paragraph 0045 teaches a second oxide layer 32 (formed of aluminum oxide) above a first oxide layer 30).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Shimizu into the method of Suzuki by forming a second oxide layer provided above the first oxide layer. The ordinary artisan would have been motivated to modify Suzuki in the manner set forth above for at least the purpose of suppressing current collapse and improving the reliability of the device (Shimizu, paragraph 0089).
With respect to the limitation “a junction interface between the first oxide layer and the second oxide layer, wherein an oxygen area density of the first oxide layer is lower than an oxygen area density of the second oxide layer”, Suzuki in view of Shimizu fails to specifically speak to this. However, cited reference Kanamura teaches that when the first oxide layer is composed of HfO2 and the second oxide layer is formed of Al2O3, a dipole can be produced during heat treatment due to the difference in oxygen density of the materials (Kanamura, paragraph 0044). Specifically, it is preferable when the lower oxygen density material such as HfO2 be used as the first oxide layer and a higher oxygen density material such as Al2O3 be used for the second oxide layer due to the dipole formation during heat treatment (Kanamura, paragraph 0046). Since the combination of Suzuki in view of Shimizu teaches semiconductor device with a first oxide layer of HfO2 and a second oxide layer of Al2O3 as taught in Kanamura, the oxide layers function as claimed above).
Regarding Claim 3, Suzuki in view of Shimizu teaches the semiconductor device according to claim 1, wherein the first oxide layer and the second oxide layer are both amorphous (Shimizu, Paragraph 0113 and 0115 teach the first (28) and second (30) oxide layers can be amorphous).
Regarding Claim 9, Suzuki in view of Shimizu teaches a method of manufacturing the semiconductor device according to claim 1, comprising:
forming the first oxide layer and the second oxide layer (Shimizu, Fig. 1, first oxide layer 30 and second oxide layer 32);
and performing a heat treatment within a temperature range in which the first oxide layer and the second oxide layer do not crystallize (Shimizu, paragraph 0131 teaches that heat treatments that cause crystallization lead to current collapse. Paragraph 0132 teaches it is preferrable to suppress crystallization during heat treatment.)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in ivew of Shimizu as applied to claims 1, 3, and 9 above, and further in view of Li (US Patent Pub 20200328297 A1).
Regarding Claim 4, Suzuki in view of Shimizu teaches the semiconductor device according to claim 1.
Suzuki in view of Shimizu fails to teach the semiconductor device wherein the first oxide layer contains nitrogen.
However, Li teaches a HEMT semiconductor device wherein the first oxide layer contains nitrogen (Li, paragraph 0059 teaches first oxide layer 510 can be formed of silicon oxynitride. Fig. 6 utilizes the same passivation layer but changes the label to 610).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Li into the method of Suzuki in view of Shimizu by forming the HEMT device wherein the first oxide layer contains nitrogen. The ordinary artisan would have been motivated to modify Suzuki in view of Shimizu in the manner set forth above for at least the purpose of protecting the device structure underneath the passivation layer (Li, paragraph 0078).
Allowable Subject Matter
Claims 5-8 and 10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 5, the prior art fails to disclose or suggest the device as claimed.
Specifically, the prior art fails to teach “a third oxide layer provided above the second oxide layer, a fourth oxide layer provided above the third oxide layer, and a fifth oxide layer provided above the fourth oxide layer”.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-4, and 9 have been considered but are moot in view of the new grounds of rejection as applied above.
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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