Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 4, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du et al. (CN 104299999 A) in view of Shimizu et al. (US Patent Pub 20180204916).
Regarding Claim 1, Du teaches a semiconductor device comprising:
a first nitride semiconductor layer (Du, Fig. 2, first nitride semiconductor layer 103);
a second nitride semiconductor layer provided above the first nitride semiconductor layer and forming a two-dimensional electron gas between the first nitride semiconductor layer and thereof (Fig. 2, second nitride semiconductor layer 104. Paragraph 0005 (see provided machine translation) teaches the heterojunction between 103 (GaN) and 104 (AlGaN) has a two-dimensional electron gas between them);
a source electrode provided above the second nitride semiconductor layer and electrically connected to the two-dimensional electron gas (Fig. 2, source electrode 106. 106 is above 104 and electrically connected to the two-dimensional electron gas);
a drain electrode provided above the second nitride semiconductor layer and electrically connected to the two-dimensional electron gas (Fig. 2, drain electrode 107. 107 is electrically connected to the two-dimensional electron gas);
a gate electrode provided above the second nitride semiconductor layer and arranged between the source electrode and the drain electrode (Fig. 2, gate electrode 108);
and a first oxide layer provided above the second nitride semiconductor layer and arranged only between the gate electrode and the source electrode (Fig. 2, first oxide layer 201 arranged only between gate electrode 108 and source electrode 106).
Du fails to teach a protective film provided above the second nitride semiconductor layer and arranged between the gate electrode and the drain electrode (Fig. 11, protective film 34) and a second oxide layer provided above the first oxide layer (Fig. 11, second oxide layer 32).
However, Shimizu teaches a protective film provided above the second nitride semiconductor layer and arranged between the gate electrode and the drain electrode, as well as teaches a second oxide layer provided above the first oxide layer (Shimizu, Fig. 1, protective film 34 and second oxide layer 30 above a first oxide layer (28 is aluminum oxide). Paragraph 0067 teaches 30 is silicon oxide. Du, paragraph 0013 (see provided machine translation) teaches first oxide layer 201 can be Si02, Si3N, Al203, HfO2 and TiO2.
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Shimizu into the method of Du by forming a protective film provided above the second nitride semiconductor layer and arranged between the gate electrode and the drain electrode and a second oxide layer provided above the first oxide layer. The ordinary artisan would have been motivated to modify Du in the manner set forth above for at least the purpose of suppressing current collapse and improving the reliability of the device (Shimizu, paragraph 0089).
With respect to the limitation “a junction interface between the first oxide layer and the second oxide layer, wherein an oxygen area density of the first oxide layer is lower than an oxygen area density of the second oxide layer”, Shimizu and Du fail to specifically speak to this. However, cited reference Kanamura teaches that when the first oxide layer is composed of HfO2 and the second oxide layer is formed of Al2O3, a dipole can be produced during heat treatment due to the difference in oxygen density of the materials (Kanamura, paragraph 0044). Specifically, it is preferable when the lower oxygen density material such as HfO2 be used as the first oxide layer and a higher oxygen density material such as Al2O3 be used for the second oxide layer due to the dipole formation during heat treatment (Kanamura, paragraph 0045). Since the combination of Du in view of Shimizu teaches semiconductor device with a first oxide layer of HfO2 and a second oxide layer of Al2O3 as taught in Kanamura, the oxide layers function as claimed above).
Regarding Claim 3, Du in view of Shimizu teaches the semiconductor device according to claim 1, wherein the first oxide layer and the second oxide layer are both amorphous (Shimizu, Paragraph 0113 and 0115 teach the first (28) and second (30) oxide layers can be amorphous).
Regarding Claim 4, Du in view of Shimizu teaches the semiconductor device according to claim 1, wherein the first oxide layer contains nitrogen (Du, paragraph 0013 (see provided machine translation) teaches first oxide layer 201 can contain nitrogen. Silicon Nitride is taught as one of the alternative materials).
Regarding Claim 9, Du in view of Shimizu teaches a method of manufacturing the semiconductor device according to claim 1, comprising the steps of:
forming the first oxide layer and the second oxide layer (Shimizu, Fig. 1, first oxide layer 28 and second oxide layer 30);
and performing a heat treatment within a temperature range in which the first oxide layer and the second oxide layer do not crystallize (Shimizu, paragraph 0131 teaches that heat treatments that cause crystallization lead to current collapse. Paragraph 0132 teaches it is preferrable to suppress crystallization during heat treatment.)
Allowable Subject Matter
Claims 5-8 and 10 are objected to as being depended upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/V.R.G./
Examiner, Art Unit 2899
/JOHN M PARKER/Examiner, Art Unit 2899