Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REQUIREMENT FOR UNITY OF INVENTION
As provided in 37 CFR 1.475(a), a national stage application shall relate to one invention only or to a group of inventions so linked as to form a single general inventive concept (“requirement of unity of invention”). Where a group of inventions is claimed in a national stage application, the requirement of unity of invention shall be fulfilled only when there is a technical relationship among those inventions involving one or more of the same or corresponding special technical features. The expression “special technical features” shall mean those technical features that define a contribution which each of the claimed inventions, considered as a whole, makes over the prior art.
The determination whether a group of inventions is so linked as to form a single general inventive concept shall be made without regard to whether the inventions are claimed in separate claims or as alternatives within a single claim. See 37 CFR 1.475(e).
When Claims Are Directed to Multiple Categories of Inventions:
As provided in 37 CFR 1.475 (b), a national stage application containing claims to different categories of invention will be considered to have unity of invention if the claims are drawn only to one of the following combinations of categories:
(1) A product and a process specially adapted for the manufacture of said product; or
(2) A product and a process of use of said product; or
(3) A product, a process specially adapted for the manufacture of the said product, and a use of the said product; or
(4) A process and an apparatus or means specifically designed for carrying out the said process; or
(5) A product, a process specially adapted for the manufacture of the said product, and an apparatus or means specifically designed for carrying out the said process.
Otherwise, unity of invention might not be present. See 37 CFR 1.475 (c).
Restriction is required under 35 U.S.C. 121 and 372.
This application contains the following inventions or groups of inventions which are not so linked as to form a single general inventive concept under PCT Rule 13.1.
In accordance with 37 CFR 1.499, applicant is required, in reply to this action, to elect a single invention to which the claims must be restricted.
Group I, claim(s) 1-18, drawn to a process of exposing and developing a bilayer resist.
Group II, claim(s) 19-20, drawn to a computer device/medium for controlling the exposure and development or a resist bilayer
The groups of inventions listed above do not relate to a single general inventive concept under PCT Rule 13.1 because, under PCT Rule 13.2, they lack the same or corresponding special technical features for the following reasons:
The examiner points to the “X” reference (JP 2008171859) cited in the international search report of 9/30/2025. Any feature which unites the inventions fails to confer patentability.
During a telephone conversation with Charles W. Gray on 5/18/2026 a provisional election was made with traverse to prosecute the invention of group I, claims 1-18. Affirmation of this election must be made by applicant in replying to this Office action. Claims 19-20 withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
The examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined.
In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “the negative photoresist includes …..or positive X-ray photoresist”. (emphasis added) This is a similar recitation to that in the prepub of the instant specification at [0044]. Is this an error ?
In claims 1 and 7, the heating after exposure is a baking, not a drying as the solvent has already been removed by the drying steps after the
In claim 1, at line 15, please replace “merely” with - - only- -.
In claim 17, at line 18, please replace “merely” with - - only- -.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,4-6,8,9-13 and 15-17 are rejected under 35 U.S.C. 103 as obvious over Park CN 101989046, in view of Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119.
Park CN 101989046 (machine translation attached) teaches the deposition of a positive resist (510), the coating of a transparent layer (520), the coating a negative resist (530), the exposure using the mask, the development of the negative resist and portions of the transparent layer to yield the structure illustrated in figure 13.
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The development of the positive resist to remove the portion between the unexposed (513) and exposed (512) regions. Removing the remaining negative resist (530) to yield the structure of figure 14.
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The pattern of the remaining resist is then transferred to the substrate. with etching The resist is then removed. The positive resist can be a PMMA or diazoquinine (DQN) resist with the developer being KOH, TMAH, ketone or another alkali developer. The negative resist can be a b-rubber (butadiene ?) resist with the developer being xylene. The substrate can include a dielectric film, a metal film, a silicon film or a single crystal silicon substrate [0046-0055]. The resist can be spin coated and the thickness of the resist coating is dependent upon the photoresist type/viscosity and the rotation speed. [0006,0035,0039] . The removal of solvent is disclosed by baking at 80-110 degrees C for 50-80 seconds [0033,0036,0040]. The exposure can use I-1ine wavelength of 365nm as exposure light line, the thickness of the photoresist with wavelength of 248nm (KrF) excimer laser or wavelength of 193nm nm argon-fluorine (ArF) [0039]. Referring to FIG. 16, in one embodiment of step S5. The photoresist layer 500 of positive photoresist 510 and the transparent material layer 520, using plasma etching method on a substrate 300 to form a pattern 600. the pattern 440 to be transferred is transferred to the substrate 300, the etching gas and the substrate 300 relative to the material, such as by chlorine (Cl2), hydrogen bromide (HBr), one kind of or the combination of hydrogen chloride (HCL) etching the silicon substrate. Besides, it also can adopt other etching method, the technical personnel should be understood, in step S5 the specific etching method and etchant does not influence the invention idea of the present invention. [0053].
Mori et al. JP 2013080869 (machine translation attached) in figure 1 teaches a substrate (10) with a lower resist layer (12) such as a KrF positive resist, provided by spraying or spin coating and pre-baked. This is then coated with a second resist layer (14), such as an ArF resist using spin coating or spraying followed by drying. The resists are both exposed to ArF light through a phase shift mask (50) and the unexposed (and underexposed) regions of the (upper) negative resist are removed using acetone or TMAH as the developer to yield the pattern in figure 3. This is then overcoated with a metal layer (16) and the remaining (exposed portions) upper resist and the overlying portion of the upper, negative resist is removed using a solvent (lift off process). The result is exposed using a polarized KrF laser to form partially exposed regions (64) (about 10 nm wide) at the edges of the metal layer (plasmon/near field effect discussed) and the metal layer is removed by dry etching to yield the structure of figure 7. The partially exposed areas are then removed using TMAH or the like as the developer to yield the structure illustrated in figure 8. This is then used to deposit wiring layer (22) as in figure 9 and then the remaining resist and the overlying/excess metal deposited to form the wiring layer is removed by dissolving the resist using TMAH (lift off) yielding 10 nm wide wiring with a separation of 20-30 nm [0011-0023].
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Numerical values such as the material, shape, and thickness of each component in each embodiment described above may be changed as appropriate. Moreover, you may combine a part or all of each embodiment. For example, the combination of the resist material, the positive and negative types of the resist material, the exposure light, the etching solution, the etching gas, and the like may be changed as appropriate [0053]. In the above-described embodiment, the resist is exposed by the ArF excimer laser and the KrF excimer laser. However, the resist may be exposed by a laser such as an F2 laser that outputs laser light having a wavelength of 157 nm [0056]. Next, as shown in FIG. 26, in the deactivation stage, the region exposed from the opening 218 of the metal layer 216 in the lower resist 212 is deactivated. Thereby, hydrogen ions in the region in the lower layer resist 212 generated by exposure are removed. An example of the deactivation method is cleaning of the exposed region 226 exposed from the opening 218 with water. Thereby, the hydrogen ions in the exposed region 226 are removed. As another example of the deactivation method, the exposed region 226 may be washed with warm water. As a result, the hydrogen ion is removed and the object to be processed is heated, so that the exposed region 226 of the lower layer resist 212 can be post-baked. As another example of the deactivation method, the exposed region 226 of the lower layer resist 212 may be exposed to an alkaline gas, for example, ammonia gas. Thereby, hydrogen ions in the exposed region 226 are neutralized [0049]. The use of wet etching or dry etching using reactive ion etch with Cl2, BCl3, SiCl4 to remove metal is disclosed at [0020]. The use of vapor/vacuum deposition to deposit the metal layer is disclosed [0016,0022].
Tanigawa et al. JP H06112119 (machine translation attached), teaches describes in the example with respect to figure 1, a silicon substrate (1), coated with a 1.07 micron o-quinonediazide positive resist (2) using spin coating and prebaking, a 0.4 micron PVA intermediate layer (3) which is spin coated and dried and a 0.34 micron negative chemically amplified photoresist (24) which is applied by spin coating and drying. This is then exposed using a mask (25) and 365 nm light. The upper resist has a higher sensitivity than the lower resist. The sensitivity of the upper resist can be 10-10 mJ/cm2 and the lower resist sensitivity is 80-170 mJ/cm2. This was then post baked and developed in ethyl cellosolve acetate or another organic solvent such as acetone, isopropanol, ethyl, butyl ketone or the like. The patterned upper layer acts as a phase shifter mask pattern during a flood/blanket exposure with a phase change of p/2 or 3p/2. The exposure uses an i-line 365 nm). The upper resist and PVA layer are then removed by lift off using water. The lower resist was then developed in TMAH a post baked. This yielded a pattern with 0.15 resist patterns, separated by 0.2 microns and a height of 0.95 microns. The thickness of the lower resist layer can be 0.6 to 1.2 microns, the thickness of the intermediate layer can be 0-.08-1 micron. [0013-0020].
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The post exposure bake at 60 degrees C for 60 seconds, followed by development in TMAH is disclosed [0020].
Park CN 101989046 does not describe wet etching or material deposition techniques or the post exposure baking of photoresists or exemplify the processes where the full range of substrate is used, the full range of exposure means is used or the specific drying conditions
With respect to claims 1,2,4,6-13 and 15-17 , it would have been obvious to one skilled in the art to modify the process taught with respect to figures 13-17 at [0047-0055] by coating each of the resists using spin coating to control the thickness as discussed at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed at [0033,0036,0040] where the exposure using an i-line as disclosed at [0039] and to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C with a reasonable expectation of forming a useful etched substrate.
Alternatively with respect to claims 1,2,4,6-13 and 15-17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 13-17 at [0047-0055] by coating each of the resists using spin coating to control the thickness as discussed at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed at [0033,0036,0040] where the substrate can include a dielectric film, a metal film, a silicon film or a single crystal silicon substrate as disclosed at [0046-0055] ] and to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C with a reasonable expectation of forming a useful etched substrate.
Alternatively with respect to claims 1,2,4,6-13 and 15-17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 13-17 at [0047-0055] by coating each of the resists using spin coating to control the thickness as discussed at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed at [0033,0036,0040] where the exposure using an i-line as disclosed at [0039] and where the substrate can include a dielectric film, a metal film, a silicon film or a single crystal silicon substrate as disclosed at [0046-0055] ] and to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020] and depositing metal using vapor deposition as taught at [0016,0022] of Mori et al. JP 2013080869 rather than etching as this is a known alternative to use of the fine resist pattern with a reasonable expectation of forming a useful patterned substrate.
Alternatively with respect to claims 1,2,5-13 and 15-17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 13-17 at [0047-0055] by coating each of the resists using spin coating to control the thickness as discussed at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed at [0033,0036,0040] where the exposure using an KrF laser or ArF laser as disclosed at [0039] and to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C with a reasonable expectation of forming a useful etched substrate. ArF and KrF lasers are pulsed lasers with nanosecond pulsewidths and the examiner has interpreted the teachings as each pulse being an individual exposure, so the use of these lasers in the disclosed process yields multiple exposures. These are also considered to be deep UV exposure sources.
Alternatively with respect to claims 1,2,5-13 and 15-17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 13-17 at [0047-0055] by coating each of the resists using spin coating to control the thickness as discussed at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed at [0033,0036,0040] where the exposure using an KrF laser or ArF laser as disclosed at [0039] and where the substrate can include a dielectric film, a metal film, a silicon film or a single crystal silicon substrate as disclosed at [0046-0055] and to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C with a reasonable expectation of forming a useful etched substrate. ArF and KrF lasers are pulsed lasers with nanosecond pulsewidths and the examiner has interpreted the teachings as each pulse being an individual exposure, so the use of these lasers in the disclosed process yields multiple exposures. These are also considered to be deep UV exposure sources.
Alternatively with respect to claims 1,2,4-13 and 15-17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 13-17 at [0047-0055] by coating each of the resists using spin coating to control the thickness as discussed at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed at [0033,0036,0040] where the exposure using an i-line, KrF laser or ArF laser as disclosed at [0039] and where the substrate can include a dielectric film, a metal film, a silicon film or a single crystal silicon substrate as disclosed at [0046-0055] and to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C and to etch using wet etching, rather than the dry reactive ion etching with Cl2 which is taught at equivalent at [0020] of Mori et al. JP 2013080869 with a reasonable expectation of forming a useful etched substrate. ArF and KrF lasers are pulsed lasers with nanosecond pulsewidths and the examiner has interpreted the teachings as each pulse being an individual exposure, so the use of these lasers in the disclosed process yields multiple exposures and the i-line exposure is considered to be a single, continuous exposure. These are also considered to be deep UV exposure sources.
Alternatively with respect to claims 1,2,4-13 and 15-17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 13-17 at [0047-0055] by coating each of the resists using spin coating to control the thickness as discussed at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed at [0033,0036,0040] where the exposure using an i-line, KrF laser or ArF laser as disclosed at [0039] and where the substrate can include a dielectric film, a metal film, a silicon film or a single crystal silicon substrate as disclosed at [0046-0055] and to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C and depositing metal using vapor deposition as taught at [0016,0022] of Mori et al. JP 2013080869 rather than etching as this is a known alternative to use of the fine resist pattern with a reasonable expectation of forming a useful patterned substrate. ArF and KrF lasers are pulsed lasers with nanosecond pulsewidths and the examiner has interpreted the teachings as each pulse being an individual exposure, so the use of these lasers in the disclosed process yields multiple exposures and the i-line exposure is considered to be a single, continuous exposure. These are also considered to be deep UV exposure sources.
With respect to claim 8, the examiner holds that while the resists disclosed are used with excimer laser or UV exposure, they are inherently sensitive to EUV, X-ray, e-beam and ion-beams, so they meet the limitations of claim 8, which does not require any particular exposure be used.
With respect to claim 10, the features formed by the masked UV projection exposure are in the 1-1000 micron range used to form useful semiconductor devices.
The KOH, TMAH or other alkali developers result in positive tone images from “positive” resists, while organic solvents, such as ketone, which are similar to the resist coating solvent, yield negative tone images from “positive” resists.
Claims 1,2,4-13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119.
Nakamura JP 2008171859 (cited by applicant 10/29/2024, machine language translation attached to this action) describes a second embodiment with respect to figure 3, a substrate (1) with a processing layer (2), a positive (first) resist (3) and a negative (second) resist (4). Both of the resists are exposed using the mask (5) to form exposed regions (320/420), weakly exposed regions (310/410, formed by diffraction of the light by the edge of the mask pattern) and strongly exposed regions. The second/negative resist is then weakly developed to remove the unexposed areas of the second/negative resist. An etch process is then used to remove the weakly exposed (410) areas of the second/negative resist. The exposed portion (320) of the first/positive resist is removed using a weak development. The processing of the areas (21) of the processing layer not covered by the resist (310) is then performed and the remaining resist(s) stripped/removed [0017].
In the fourth embodiment (illustrated in figure 5), a substrate (16) having a processing target layer (26) is coated with a positive resist (36), Then a negative resist (46) is applied. These are exposed through a mask (5) to form strongly exposed areas (462/362, due to diffraction of light at the edge of the mask pattern), weakly exposed areas (461/361) and unexposed areas. The second/negative resist was strongly developed to remove the unexposed and weakly exposed portions of the negative resist. A second development was then used to remove the weakly exposed regions (361) of the positive resist. The desired processing of the processing layer is then performed in areas (261) not protected by the resists. The remaining resists is then stripped/removed [0020].
In the manufacture of a semiconductor integrated circuit, a processing target layer is formed on the surface of a wafer to be a substrate, a resist is applied, and pattern exposure is performed using such a mask to form a resist pattern. Then, the processing target layer is processed. An example of the processing target layer is an insulating film layer (SiO .sub.2 is generally used). An insulating film is formed on the substrate, a resist is coated on the insulating film layer, a mask pattern is exposed and developed to form a resist pattern, and the insulating layer film is removed by etching from the opening where the resist is not left. To do. Further, for example, a semiconductor layer is formed on the substrate as a processing target layer, then a resist pattern is formed, and impurities are diffused to form an impurity semiconductor region. Alternatively, as a processing target layer, a conductive film layer is formed on the substrate, a mask pattern is exposed to form a resist pattern, and then etched to form a wiring layer. In this manner, various resist patterns are formed, and processing such as etching, thermal oxidation treatment, impurity introduction, and thin film formation is repeated to manufacture an integrated circuit. This is also used and manufactured for electronic devices other than integrated circuits [0004]. As described above, a desired processed substrate can be obtained. Such a resist pattern is formed using this substrate as a wafer, and etching, thermal oxidation treatment, impurity introduction, thin film formation, etc. are performed as desired processing. The integrated circuit can be manufactured repeatedly. Such a process can be used and manufactured for other electronic devices other than integrated circuits [0021] As an example of a semiconductor integrated circuit as a main element, miniaturization of a mask pattern used for lithography and shortening of the wavelength of exposure light are being promoted. For example, phase shift masks (Patent Documents 1 and 2), proximity effect correction masks (OPPCPC (optical proximity correction)), etc., have been developed as masks that mainly reduce the effects of diffraction phenomena and advance miniaturization. The use of KrF excimer laser (wavelength 248 nm), ArF excimer laser (wavelength 193 nm), and then F2 excimer laser (wavelength 157 nm) has been proposed and developed. In recent years, an extreme ultraviolet exposure mask using reflected light has been developed as a mask for such a short wavelength. In particular, in pattern formation with a line width of 65 nm or less, an immersion lithography method that fills the gap between the lens and the wafer to be exposed with a medium having a higher refractive index than air and improves the effective resolution has attracted attention. According to this method, it is expected that a pattern of 65 nm or less, which has been difficult to form with a conventional ArF excimer laser, can be formed [0003]. In the resist pattern forming method of the present invention and the method of manufacturing an electronic device using the resist pattern, a fine resist pattern is formed by exposure using a diffraction phenomenon and processed into a fine pattern corresponding to the pattern. Manufacturing electronic devices. Therefore, by using a phase shift mask or an OPC mask and combining an optical system for exposure to extreme ultraviolet rays or liquid immersion with the method of the present invention, further fine processing can be performed [0025].
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Further, in the resist pattern forming method of the present invention, a linear pattern is formed at a portion corresponding to the boundary portion of the mask pattern. FIG. 6 is a partial explanatory view showing an example of the mask pattern 51 according to the present application and an example of the resist pattern 52 formed by the method of the present invention using the mask pattern 51 in plan view. A resist pattern 52 is formed at a position corresponding to the boundary of the pattern as shown in FIG. 6B with respect to the mask 5 on which the mask pattern 51 having the width A and the inter-pattern distance B of FIG. 6A is formed. . Therefore, if the mask 5 is a line pattern 51, a line segment pattern 52 can be formed in a ring shape as a resist. On the other hand, FIG. 7 is an explanatory view showing an example in which the resist pattern is formed in a linear pattern that does not have a ring shape. The pattern 55 of the mask 50 in FIG. 7A has a pattern width A .sub.1 substantially equal to the width of the resist pattern 52 in FIG. 6B. If the resist pattern 54 is formed by using the mask 50 on which such a pattern 55 is formed, as shown in FIG. 7B, a linear resist pattern that does not form a ring shape due to contact with the contour line pattern. 54 is formed. In addition, various rectangular resist patterns can be formed by adjusting the length of the mask pattern in FIG. Further, by reducing the inter-pattern distance B .sub.1 , the number of touching patterns can be increased, and a pattern having a large area can be formed [0022].
Nakamura JP 2008171859 does not teach spin coating and drying of the resists.
With respect to claims 1,2,5-13 and 17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 3 and 5 as discussed at [0017,0020] of Nakamura JP 2008171859 by coating each of the resists using spin coating to control the thickness as discussed in Park CN 101989046 at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed in Park CN 101989046 at [0033,0036,0040] where the exposure uses masked exposure with KrF excimer laser (wavelength 248 nm), ArF excimer laser (wavelength 193 nm), F2 excimer laser (wavelength 157 nm) or extreme ultraviolet light (EUV/soft X-ray) to form patterns as small as 65 nm as discussed at [0003] of Nakamura JP 2008171859 to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C and then etching or forming/depositing a thin film as discussed in Nakamura JP 2008171859 at [0021], wet etching taught at [0020] of Mori et al. JP 2013080869 or deposition using vapor deposition as taught at [0016,0022] of Mori et al. JP 2013080869 with a reasonable expectation of forming a useful patterned substrate.
With respect to claims 1,2,4,6-13 and 17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 3 and 5 as discussed at [0017,0020] of Nakamura JP 2008171859 by coating each of the resists using spin coating to control the thickness as discussed in Park CN 101989046 at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed in Park CN 101989046 at [0033,0036,0040] where the exposure uses extreme ultraviolet exposure masking to form patterns as small as 65 nm as discussed at [0003] of Nakamura JP 2008171859 to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C and then etching or forming a thin film as discussed in Nakamura JP 2008171859 at [0021] wet etching taught at [0020] of Mori et al. JP 2013080869 or deposition using vapor deposition as taught at [0016,0022] of Mori et al. JP 2013080869 with a reasonable expectation of forming a useful patterned substrate.
With respect to claims 1,2,4-13 and 17, it would have been obvious to one skilled in the art to modify the process taught with respect to figures 3 and 5 as discussed at [0017,0020] of Nakamura JP 2008171859 by coating each of the resists using spin coating to control the thickness as discussed in Park CN 101989046 at [0006,0035,0039] and dried by baking at 80-110 degrees as disclosed in Park CN 101989046 at [0033,0036,0040] where the exposure uses masked exposure with KrF excimer laser (wavelength 248 nm), ArF excimer laser (wavelength 193 nm), F2 excimer laser (wavelength 157 nm) to form patterns as small as 65 nm as discussed at [0003] of Nakamura JP 2008171859 to post bake the resist after exposure as disclosed by Mori et al. JP 2013080869 at [0049] and Tanigawa et al. JP H06112119 at [0020], who teaches this post bake at 60 degrees C and then etching or forming a thin film on a dielectric film, a metal film, a silicon film or a single crystal silicon substrate as disclosed at [0046-0055] of Park CN 101989046 as discussed in Nakamura JP 2008171859 at [0021], wet etching taught at [0020] of Mori et al. JP 2013080869 or deposition using vapor deposition as taught at [0016,0022] of Mori et al. JP 2013080869 with a reasonable expectation of forming a useful patterned substrate.
with a reasonable expectation of forming a useful patterned substrate. ArF, KrF and F2 lasers are pulsed lasers with nanosecond pulsewidths and the examiner has interpreted the teachings as each pulse being an individual exposure, so the use of these lasers in the disclosed process yields multiple exposures. These are also considered to be deep UV exposure sources.
Claims 1-13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119, further in view of Aton 20090169832.
Aton 20090169832 teaches spin coating of positive or negative resist using spin coating at 500-3000 RPM [0043].
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 describes spin coating, but does not teach spin coating velocities within the 500-8000 RPM range.
In addition to the basis above, it would have been obvious t preform the spin coating in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 by spin coating the positive or negative resists at 500-3000 RPM as is known in the art as evidenced at [0043] of Aton 20090169832 for the necessary time to achieve the desired thickness with a reasonable expectation of forming useful resist coatings and useful patterns substrates as the end of the process.
Claims 1,2, and 5-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119, further in view of Takahashi et al. JP 2001237174.
Takahashi et al. JP 2001237174 (machine translation attached) teaches the EUV exposure apparatus shown in FIG. 9 reduces the EUV light image reflected from the reflective mask onto a semiconductor wafer coated with a photoresist for EUV lithography (a positive or negative type photoresist having photosensitivity in the EUV region) [0064].
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 discloses the use of EUV exposures, but does not teach that the (photo)mask is reflective
In addition to the basis above, it would have been obvious to perform the exposures in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 by using an EUV exposure with a reflective (photo)mask as is known in the art as evidenced in Takahashi et al. JP 2001237174 with a reasonable expectation of forming an exposed resist coating and useful patterns substrates as the end of the process.
Claims 1,2,4-13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119, further in view of Mani 20140315133.
Mani 20140315133 teaches that with a positive-tone resist, the portions that are exposed to the radiation through the transparent regions in the mask become soluble in the developer solution, and in a negative-tone resist the portions that are exposed to the radiation through the transparent regions in the mask become insoluble in the developer solution. The radiation used is generally ultra-violet light (UV) or extreme UV light (EUV). The positive-tone and the negative tone resists are generally sensitive to different wavelength regions of the radiation. X-rays, ion beams or electron beams are also used for exposure, generally for direct-write in mask-less lithographic systems and with corresponding resists.
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 discloses the use masked exposure using UV or EUV, but does not disclosed the use of direct write processes.
In addition to the basis above, it would have been obvious to perform the exposures in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 by using direct writing with beams of X-rays, ions or electrons rather than an exposure using a (photo)maks based upon the equivalence established in Mani 20140315133 with a reasonable expectation of forming an exposed resist coating and useful patterns substrates as the end of the process.
Claims 1,2,4-13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119, further in view of Kramer et al. 20130213469, Ho et al. 20040124513 and/or Liao et al. CN 112151602.
Kramer et al. 20130213469 teaches patterning processes used in the manufacture of semiconductor solar cells including such as but not limited to blanket metal deposition (for example, by a Physical-Vapor Deposition or PVD technique such as plasma sputtering, evaporation, thermal or arc plasma spray, or ion beam deposition; or by using an electrochemical deposition process such as plating) followed by pattern formation using pulsed laser metal ablation or a combination of lithography (for instance, using screen printing of a patterned etch resist layer) and subsequent etching of metal and stripping of the resist layer [0511]
Ho et al. 20040124513 teaches an etching process is performed on the second surface 104 of the semiconductor substrate 100 to remove a portion of the semiconductor substrate 100 and a portion of the insulating layer 110 so as to form a plurality of via holes 140 penetrating the semiconductor substrate 100 and the insulating layer 110, and expose the second bonding pads 132. During the etching process, a first photoresist layer can be formed on the second surface 104 firstly (nor shown). Then the etching process is performed by using ion beam etching, reactive ion etching, chemical etching, laser enhanced etching, ultraviolet enhanced etching or electrochemical etching to remove a portion of the semiconductor substrate 100 and a portion of the insulating layer 110. Finally, the first photoresist layer is removed [0019]
Liao et al. CN 112151602 (Machine translation attached) teaches the use of photoresist in forming semiconductor devices. The use a various deposition techniques for depositing layers to be pattern includes chemical vapor deposition; atomic layer deposition, magnetic control sputtering or pulse laser deposition method [0061].
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 discloses performing etching or material deposition after developing the resist pattern, but does not disclose some of the specific etch or deposition processes recited in claim 11 of the instant applicant.
In addition to the basis above, it would have been obvious to perform the exposures in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 by using etching or materials deposition processes known to be useful in the photolithographic/semiconductor manufacturing arts, such as those disclosed by Kramer et al. 20130213469, Ho et al. 20040124513 and/or Liao et al. CN 112151602 with a reasonable expectation of forming a useful patterned substrate.
Claims 1,2,4-13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119, further in view of Sandstrom et al. 20200301270.
Sandstrom et al. 20200301270 teaches that the general sequence of processing steps for a typical photolithography process includes the steps of substrate preparation, a photoresist spin coat, prebake, exposure, post-exposure bake, develop. A resist strip is the final operation in the lithographic process, after the resist pattern has been transferred into the underlying layer, typically by some sort of etch process. This sequence of steps is generally performed on several tools linked together into a contiguous unit called a lithographic cluster, controlled by a computer, processor, or processing circuit [0006]. The present invention relates to a method used in a photolithographic process comprising depositing a film of Atomic Layered Deposition (ALD) Al.sub.2O.sub.3 on a photomask, subjecting said film of Al.sub.2O.sub.3 on the photomask to a plasma treatment and then irradiating the deposited film of ALD Al.sub.2O.sub.3 on the coaled photomask at a wavelength of 193 nm [0030].
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 does not disclose the controlling of the various photolithographic steps in the processes.
In addition to the basis above, it would have been obvious to perform the exposures in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869 and Tanigawa et al. JP H06112119 by linking the various chambers/tools together in a photolithographic cluster and controlling them using a circuit or computer program as is known in the art of Sandstrom et al. 20200301270 at [0006] to automate the photolithographic process with a reasonable expectation of forming a useful patterned substrate.
Claims 1-13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Aton 20090169832, further in view of Sandstrom et al. 20200301270
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Aton 20090169832 does not disclose the controlling of the various photolithographic steps in the processes.
In addition to the basis above, it would have been obvious to perform the exposures in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Aton 20090169832 by linking the various chambers/tools together in a photolithographic cluster and controlling them using a circuit or computer program as is known in the art of Sandstrom et al. 20200301270 at [0006] to automate the photolithographic process with a reasonable expectation of forming a useful patterned substrate.
Claims 1,2 and 4-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Takahashi et al. JP 2001237174, further in view of Sandstrom et al. 20200301270
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Takahashi et al. JP 2001237174 does not disclose the controlling of the various photolithographic steps in the processes.
In addition to the basis above, it would have been obvious to perform the exposures in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Takahashi et al. JP 2001237174 by linking the various chambers/tools together in a photolithographic cluster and controlling them using a circuit or computer program as is known in the art of Sandstrom et al. 20200301270 at [0006] to automate the photolithographic process with a reasonable expectation of forming a useful patterned substrate.
Claims 1,2,4-13 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view of Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Sandstrom et al. 20200301270, further in view of Kramer et al. 20130213469, Ho et al. 20040124513 and/or Liao et al. CN 112151602.
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Sandstrom et al. 20200301270 discloses performing etching or material deposition after developing the resist pattern, but does not disclose some of the specific etch or deposition processes recited in claim 11 of the instant applicant.
In addition to the basis above, it would have been obvious to perform the exposures in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119 and Sandstrom et al. 20200301270 by using etching or materials deposition processes known to be useful in the photolithographic/semiconductor manufacturing arts, such as those disclosed by Kramer et al. 20130213469, Ho et al. 20040124513 and/or Liao et al. CN 112151602 with a reasonable expectation of forming a useful patterned substrate.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura JP 2008171859, in view Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119, Takahashi et al. JP 2001237174 and Sandstrom et al. 20200301270 , further in view of Aton 20090169832
The combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119, Takahashi et al. JP 2001237174 and Sandstrom et al. 20200301270 describes spin coating, but does not teach spin coating velocities within the 500-8000 RPM range.
In addition to the basis above, it would have been obvious t preform the spin coating in the processes rendered obvious by the combination of Nakamura JP 2008171859, Park CN 101989046, Mori et al. JP 2013080869, Tanigawa et al. JP H06112119, Takahashi et al. JP 2001237174 and Sandstrom et al. 20200301270 by spin coating the positive or negative resists at 500-3000 RPM as is known in the art as evidenced at [0043] of Aton 20090169832 for the necessary time to achieve the desired thickness with a reasonable expectation of forming useful resist coatings and useful patterns substrates as the end of the process.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP 3091886 (machine language attached, teaches with respect to figures 1a-d, a substrate (1) coated with a lower resist (2) and a positive resist (3) where the top resist has an interferometric thickness equal to kl. The top resist is exposed and developed to yield the pattern in 1b (the lower resist is insoluble in the developer for the top resist). The result is flood exposed at wavelength l. The upper resist is then removed by a developer because it has been entirely exposed. The lower resist is then developed. When the lower resist is a positive resist it yields the fine pattern corresponding to the edges of the top resist where the resist was under exposed (figure 1c). When the lower resist is a negative resist it yields the fine pattern with openings corresponding to the edges of the top resist where the resist was under exposed (figure 1d) [0006-0013]. Since the contrast of the light intensity is generated by the interference of the light waves, there is an effect that it is possible to perform the patterning of the line width or the space smaller than the wavelength [0013]
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Kanazawa JP-H0567559 (machine translation attached) teaches using a resist as a phase shifter to form a finer pattern in the lower resist layer and patterning the underlying materials by etching.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Martin J Angebranndt whose telephone number is (571)272-1378. The examiner can normally be reached 7-3:30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark F Huff can be reached at 571-272-1385. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARTIN J. ANGEBRANNDT
Primary Examiner
Art Unit 1737
/MARTIN J ANGEBRANNDT/Primary Examiner, Art Unit 1737 May 31, 2026
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