Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-64 are pending and have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on JP2021-100118 filed on 06/16/2021 and JP2021-200445 filed on 12/09/2021.
Claim Objections
Claims 1-64 are objected to because of the following informalities:
All the claims should have “Claim” preceded by the claim number. For example: for claim 1, it should recite “Claim 1” instead of just “1”. This should be done for all other claims.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi (US 20180286910 A1 – hereinafter Kobayashi).
Regarding Claim 13, Kobayashi teaches an optical detection device (see the entire document; Fig. 4; specifically, ([0042] - [0058]), and as cited below), comprising:
a first semiconductor layer (100 – Fig. 4 – [0042]) that includes a photoelectric conversion region (elements PD – [0042]), and has one surface corresponding to a first surface (101 – [0047]) and another surface corresponding to a second surface (102 – [0047]) that is a light entrance surface;
a second semiconductor layer (200 – [0048]) that has one surface corresponding to a third surface (202 – [0049]) and another surface corresponding to a fourth surface (201 – [0049]);
a second wiring layer (220 – [0049]) overlapped with the third surface (202) of the second semiconductor layer (200);
a third wiring layer (210 – [0048]) overlapped with the fourth surface (201) of the second semiconductor layer (200);
a first wiring layer (110 – [0047]) that has one surface overlapped with the first surface (101) of the first semiconductor layer (102) and another surface overlapped with one of the second wiring layer (220) and the third wiring layer (210);
a first conductor (76 – [0054]) that includes a first material (Cu – [0058]), and penetrates the second semiconductor layer (200) in a thickness direction; and
a second conductor (73) that includes a second material (W – [0058]) different from the first material, and penetrates the second semiconductor layer (200) in the thickness direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-3, 5-6, 11-12, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over by Kobayashi.
Regarding Claim 1, Kobayashi teaches an optical detection device (see the entire document; Fig. 4; specifically, ([0042] - [0058]), and as cited below), comprising:
a first semiconductor layer (100 – Fig. 4 – [0042]) that includes a photoelectric conversion region (elements PD – [0042]), and has one surface corresponding to a first surface (101 – [0047]) and another surface corresponding to a second surface (102 – [0047]) that is a light entrance surface (from top);
a second semiconductor layer (200 – [0048]) that has one surface corresponding to a third surface (202 – [0049]) and another surface corresponding to a fourth surface (201 – [0049]);
a second wiring layer (220 – [0049]) overlapped with the third surface (202) of the second semiconductor layer (200);
a third wiring layer (210 – [0048]) overlapped with the fourth surface (201) of the second semiconductor layer (200);
a first wiring layer (110 – [0047]) that has one surface overlapped with the first surface (101) of the first semiconductor layer (102) and another surface overlapped with one of the second wiring layer (220) and the third wiring layer (210);
a first conductor (76 – [0054]) that has a first width, includes a first material (Cu – [0058]), and penetrates the second semiconductor layer (200) in a thickness direction; and
a second conductor (73) that includes a second material different from the first material (W – [0058]), and penetrates the second semiconductor layer (200) in the thickness direction.
But Kobayashi does not expressly disclose the width of the second conductor (73) having a smaller width than the width of the first conductor (76).
However, in [0094] teaches that a group of electrodes [61, 62, 65, and 66] can be formed with different widths of another group of electrodes [71-76].
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make width of the second conductor (73) smaller than the width of the first conductor (76).
An ordinary artisan would have been motivated to form the second conductor smaller than the first conductor to “normalize or reduce the costs” – [0094].
Regarding Claim 2, Kobayashi teaches the optical detection device according to claim 1, wherein one side end of the first conductor and one side end of the second conductor are respectively connected to different wires belonging to one metal layer (Fig. 4 indicates that ends on one side of 73, 76 are connected to a wiring of the wiring structure 210).
Regarding Claim 3, Kobayashi teaches the optical detection device according to claim 2, wherein the one metal layer is a metal layer included in metal layers of the third wiring layer and located closest to the second semiconductor layer (Fig. 4 indicates that ends on one side of 73, 76 are connected to a wiring of the wiring structure 210).
Regarding Claim 5, Kobayashi teaches the optical detection device according to claim 1, wherein the second conductor is provided in a region that is included in the second semiconductor layer and that overlaps, in a planar view, with a pixel region where a plurality of the photoelectric conversion regions are arranged in a matrix (Kobayashi teaches in [0056] that the through electrode 76 (first conductor) can be adapted as through electrodes 53, 57 in fig. 3, and the through electrode 73 (second conductor) can be adapted as through electrodes 54, 55 in fig. 3, and that the through electrodes 53, 57 are provided to a peripheral region PR, and the through electrodes 54, 55 are provided to a pixel region PX).
Regarding Claim 6, Kobayashi teaches the optical detection device according to claim 5, wherein the first conductor is provided in a region that is included in the second semiconductor layer and that overlaps, in the planar view, with a peripheral region that is provided outside the pixel region and that surrounds the pixel region (Kobayashi teaches in [0056] that the through electrode 76 (first conductor) can be adapted as through electrodes 53, 57 in fig. 3, and the through electrode 73 (second conductor) can be adapted as through electrodes 54, 55 in fig. 3, and that the through electrodes 53, 57 are provided to a peripheral region PR, and the through electrodes 54, 55 are provided to a pixel region PX).
Regarding Claim 11, Kobayashi teaches the optical detection device according to claim 1, wherein the first conductor contains copper, and the second conductor contains high melting metal ([0058] teaches 76 is Cu and [0058] teaches 73 is W).
Regarding Claim 12, Kobayashi teaches the optical detection device according to claim 1, comprising: a third semiconductor layer; and a fourth wiring layer that has one surface overlapped with the third semiconductor layer and another surface overlapped with the other of the second wiring layer and the third wiring layer, wherein the second semiconductor layer has a transistor constituting a readout circuit, and the third semiconductor layer has a transistor constituting a logic circuit ([0045] teaches semiconductor substrate 300 (third semiconductor layer) and a wiring structure 310 (fourth wiring layer) having one surface superimposed onto the semiconductor substrate 300 and another surface superimposed over the wiring structure 210).
Regarding Claim 15, Kobayashi teaches an electronic apparatus (see the entire document; Fig. 4; specifically, ([0042] - [0058]), and as cited below), comprising:
an optical detection device (device in Fig. 4); and
an optical system that causes the optical detection device to form an image of image light coming from a subject ([0047]), wherein the optical detection device includes
a first semiconductor layer (200 – [0048]) that includes a photoelectric conversion region (elements PD – [0042]), and has one surface corresponding to a first surface (101 – [0047]) and another surface corresponding to a second surface (102 – [0047]) that is a light entrance surface (from top),
a second semiconductor layer (200 – [0048]) that has one surface corresponding to a third surface (202 – [0049]) and another surface corresponding to a fourth surface (201 – [0049]),
a second wiring layer (220 – [0049]) overlapped with the third surface (202) of the second semiconductor layer (200),
a third wiring layer (210 – [0048]) overlapped with the fourth surface (201) of the second semiconductor layer (200),
a first wiring layer (210 – [0048]) that has one surface overlapped with the first surface (101) of the first semiconductor layer (200) and another surface overlapped with one of the second wiring layer (220) and the third wiring layer (210),
a first conductor (76 – [0054]) that has a first width, includes a first material (Cu – [0058]), and penetrates the second semiconductor layer (200) in a thickness direction, and
a second conductor (73) that includes a second material different (W – [0058]) from the first material, and penetrates the second semiconductor layer (200) in the thickness direction.
But Kobayashi does not expressly disclose the width of the second conductor (73) having a smaller width than the width of the first conductor (76).
However, in [0094] teaches that a group of electrodes [61, 62, 65, and 66] can be formed with different widths of another group of electrodes [71-76].
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make width of the second conductor (73) smaller than the width of the first conductor (76).
An ordinary artisan would have been motivated to form the second conductor smaller than the first conductor to “normalize or reduce the costs” – [0094].
Regarding Claim 16, Kobayashi teaches an optical detection device (see the entire document; Fig. 4; specifically, ([0042] - [0058]), and as cited below), comprising:
a first semiconductor layer (100 – Fig. 4 – [0042]) that includes a photoelectric conversion region (elements PD – [0042]), and has one surface corresponding to a first surface (101 – [0047]) and another surface corresponding to a second surface (102 – [0047]) that is a light entrance surface;
a second semiconductor layer (200 – [0048]) that has one surface corresponding to a third surface (202 – [0049]) and another surface corresponding to a fourth surface (201 – [0049]);
a second wiring layer (220 – [0049]) overlapped with the third surface (202) of the second semiconductor layer (200);
a third wiring layer (210 – [0048]) overlapped with the fourth surface (201) of the second semiconductor layer (200);
a first wiring layer (110 – [0047]) that has one surface overlapped with the first surface (101) of the first semiconductor layer (102) and another surface overlapped with one of the second wiring layer (220) and the third wiring layer (210);
a first conductor (76 – [0054]) that has a first width, and penetrates the second semiconductor layer (200) in a thickness direction; and
a second conductor (73) and penetrates the second semiconductor layer (200) in the thickness direction.
But Kobayashi does not expressly disclose the width of the second conductor (73) having a smaller width than the width of the first conductor (76).
However, in [0094] teaches that a group of electrodes [61, 62, 65, and 66] can be formed with different widths of another group of electrodes [71-76].
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make width of the second conductor (73) smaller than the width of the first conductor (76).
An ordinary artisan would have been motivated to form the second conductor smaller than the first conductor to “normalize or reduce the costs” – [0094].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over by Kobayashi in view of Ito et al. (US 20200035737 A1 – hereinafter Ito).
Regarding Claim 4, Kobayashi teaches claim 2 from which claim 4 depends. But. Kobayashi does not expressly disclose a barrier insulation film that is provided at a position overlapping with the wires in the thickness direction, and reduces diffusion of metal.
However, in a related art, Ito teaches an inter-layer insulative film around the bonding parts is made in a combination of a Cu diffusion barrier insulative film for preventing (or alternatively, mitigating) Cu diffusion of the Cu wirings and an insulative film without Cu diffusion barrier property (Ito – [0112]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein a barrier insulation film that is provided at a position overlapping with the wires in the thickness direction, and reduces diffusion of metal as taught by Ito into Kobayashi.
An ordinary artisan would have been motivated to integrate Ito structure into Kobayashi structure in the manner set forth above for, at least, for the obvious benefit of suppressing metal diffusion.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over by Kobayashi in view of Yamamoto et al. (US 20190326345 A1 – hereinafter Yamamoto).
Regarding Claims 7-10, Kobayashi teaches claim 1 from which claims 7-10 depend. But. Kobayashi does not expressly disclose the limitations in these claims.
However, in a related art, Yamamoto teaches in para. [0167] a through hole has a tapered shape, and that examples of the diameter of the through hole include 100 nm to 1 μm.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of the first width of the first conductor to be 1 to 5 μm as taught by Ito into Kobayashi.
An ordinary artisan would have been motivated to integrate Ito structure into Kobayashi structure in the manner set forth above for, at least, for the obvious benefit of forming different widths of conductors as appropriate.
Claims 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over by Kobayashi in view of Yajima et al. (US 20200312913 A1 – hereinafter Yajima).
Regarding Claims 24-26, Kobayashi teaches claim 16 from which claims 24-26 depend. But. Kobayashi does not expressly disclose the limitations in these claims.
However, in a related art, Yajima teaches in [0041] a semiconductor device provided with a wiring layer having a laminated structure of tantalum and copper in a wiring structure having a wiring to which a via plug is connected.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein a semiconductor device provided with a wiring layer having a laminated structure of tantalum and copper in a wiring structure having a wiring to which a via plug is connected as taught by Yajima into Kobayashi.
An ordinary artisan would have been motivated to integrate Yajima structure into Kobayashi structure in the manner set forth above for, at least, for the obvious benefit of forming laminated structure with appropriate materials ads needed.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over by Kobayashi in view of Inoue et al. (US 20130248862 A1 – hereinafter Inoue).
Regarding Claims 33, Kobayashi teaches claim 16 from which claim 33 depends. But. Kobayashi does not expressly disclose wherein the second semiconductor layer is a part of a semiconductor layer included in an SOI substrate.
However, it is well known in the art to form a semiconductor layer which is a part of an SOI substrate as is also taught by Inoue (Inoue – [0173]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein the second semiconductor layer is a part of a semiconductor layer included in an SOI substrate as taught by Inoue into Kobayashi.
An ordinary artisan would have been motivated to integrate Inoue structure into Kobayashi structure in the manner set forth above for, at least, for the obvious benefit of reduced parasitic capacitance.
Allowable Subject Matter
Claims 17-23, 27-32, 34-64 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 17: The optical detection device according to claim 16, wherein the second semiconductor layer has a first transistor including the second conductor as a gate electrode, and including, as a gate insulation film, an insulation film provided between a side surface of the second conductor and the second semiconductor layer.
Claims 18-23.
Regarding claim 27: The optical detection device according to claim 16, wherein a separation insulation film is provided between the second conductor and the second semiconductor layer, the third wiring layer has an insulation film and wires provided in the insulation film, the second conductor includes a material identical to a material of one wire of the wires included in the third wiring layer, and is provided integrally with the one wire, and the separation insulation film projects into the insulation film of the third wiring layer.
Claims 28-32 depend from claim 27.
Regarding claim 34: The optical detection device according to claim 33, wherein a plurality of the second conductors are provided, and height positions of ends of a plurality of the second conductors on the fourth surface side are equalized in the thickness direction of the second semiconductor layer.
Regarding claim 35: The optical detection device according to claim 33, comprising: an insulation layer of the SOI substrate, wherein the end of the second conductor on the fourth surface side penetrates the insulation layer.
Regarding claim 36: The optical detection device according to claim 16, wherein the third wiring layer has an insulation film, a protection insulation film laminated on the fourth surface side of the second semiconductor layer via the insulation film, and a conductor, and an end of the second conductor on the fourth surface side extends in a direction away from the fourth surface, and is connected to the conductor at a position not exceeding a lamination position of the protection insulation film.
Claims 37-40 depend from claim 36.
Regarding claim 41: The optical detection device according to claim 16, comprising: a first fixed charge film so provided as to cover an outer circumferential surface of a fifth conductor that is the one second conductor; and a second fixed charge film so provided as to cover an outer circumferential surface of a sixth conductor that is the different one second conductor, wherein the first fixed charge film and the second fixed charge film are one of a negative fixed charge film and a positive fixed charge film and the other of the negative fixed charge film and the positive fixed charge film, respectively.
Claims 42-46 depend from claim 41.
Regarding claim 47: The optical detection device according to claim 16, wherein the one second conductor has a seventh conductor located near the third surface and an eighth conductor located near the fourth surface in the thickness direction of the second semiconductor layer, and a first end that is an end of the seventh conductor and that is located near the fourth surface is connected, within the second semiconductor layer, to a second end that is an end of the eighth conductor and that is located near the third surface.
Claims 48-53 depend from claim 47.
Regarding claim 54: The optical detection device according to claim 16, wherein the first conductor includes a first material, the second conductor includes a second material different from the first material, each of the first conductor and the second conductor projects into the third wiring layer from the fourth surface, and heights of projection of the first conductor and the second conductor into the third wiring layer are different from each other.
Claims 55-57 depend from claim 54.
Regarding claim 58: The optical detection device according to claim 16, comprising: an insulation member that penetrates the second semiconductor layer in the thickness direction, wherein the optical detection device has a triple structure so formed as to surround a periphery of the second conductor by a part of the second semiconductor layer and further surround the part of the second semiconductor layer by the insulation member in a planar view.
Regarding claim 59: The optical detection device according to claim 16, wherein the second conductor has a first end that is an end on the fourth surface side, a second end that is included in the second conductor and that is an end on the third surface side, and an intermediate portion located between the first end and the second end, and the first end has a larger diameter than the intermediate portion.
Claim 60 depends from claim 59.
Regarding claim 61: The optical detection device according to claim 16, wherein each of the wiring layer that is the second wiring layer or the third wiring layer and is overlapped with the first wiring layer and the first wiring layer has a plurality of wires laminated via an insulation film, a plurality of vias extending in a lamination direction, and a plurality of reflection members, each of the vias achieves electric connection between the respective wires, or between the wires and one of the first semiconductor layer and the second semiconductor layer, and the reflection members are arranged at height positions identical to height positions of the vias in the lamination direction, and arranged in a matrix in a planar view in such a manner as to fill an area between the respective vias.
Claim 62 depends from claim 61.
Regarding claim 63: The optical detection device according to claim 16, comprising: a third semiconductor layer; a fourth wiring layer that has one surface overlapped with the third semiconductor layer and another surface overlapped with the other of the second wiring layer and the third wiring layer; and a heat dissipation path that has one end connected to a surface of the second semiconductor layer on the third semiconductor layer side and another end connected to the third semiconductor layer 80.
Claim 64 depends from claim 63
REASON FOR ALLOWANCE
Claim 14 is allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 14, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20180286910 A1 to Kobayashi) substantially teach(es) does not teach “a manufacturing method of an optical detection device, the manufacturing method comprising: forming one conductor in a semiconductor layer such that the one conductor penetrates the semiconductor layer; laminating an insulation film such that the insulation film covers one end of the one conductor; forming, from the insulation film side, a different conductor that includes a material different from a material constituting the one conductor and has a larger diameter than the one conductor such that the different conductor penetrates the semiconductor layer; and forming, from the insulation film side, a wire connected to the one conductor and a wire connected to the different conductor” as recited in claim 14. Therefore, the claim 14 is deemed patentable over the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898