Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification submitted 12/08/2023 has been accepted by the examiner.
Drawings
The drawings submitted on 12/08/2023 have been accepted by the examiner.
Information Disclosure Statements
The information disclosure statements (IDS) submitted recently have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-18, 21, 23-24, and 28-31 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Krogstrup (WO2019001753, cited in IDS dated 12/08/2023).
Regarding Claim 16, Krogstrup teaches a semiconductor device, comprising:
a substrate (104) having a surface (top);
a mesa (material 108) arranged on the surface of the substrate (shown in Fig. 1), the mesa having a perimeter (shown in Fig. 1, P3); and
one or more gate electrodes (material 112);
wherein the mesa is obtainable by selective area growth (108 is a material obtainable with that growth process), and comprises a semiconductor heterostructure for hosting a 2-dimensional electron gas or a 2-dimensional hole gas ([0064] teaches the 2DEG characteristic); and
wherein the one or more gate electrodes are configured to deplete electrically portions of the semiconductor heterostructure to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from the perimeter of the mesa (This feature essentially defines a configuration allowing a change of carrier density within the volume of the heterostructure, at a location different from the perimeter, including the two-dimensional electron or hole gas, caused by the electric field distribution generated by the gate. In other words, it defines a device geometry wherein the electric field distribution of the gate is inhomogeneous over the volume of the semiconductor heterostructure. This is the case for the side gate of D1 in a direction along the width of semiconductor 104 due to the varying distance to the gate electrode 112 in region 122 and also along a direction along the height of semiconductor 104 since the height of the semiconductor is larger than the thickness of the gate electrode.).
Regarding Claim 17, Krogstrup teaches the semiconductor device according to claim 16, wherein the semiconductor heterostructure comprises a quantum well arranged between a lower barrier and an upper barrier (2DEG has this structure).
Regarding Claim 18, Krogstrup teaches the semiconductor device according to claim 16, wherein the mesa has a width of less than or equal to 2 microns ([054] teaches within this range of dimensions).
Regarding Claim 21, Krogstrup teaches the semiconductor device according to claim 16, further comprising a superconductor component (116) arranged over the active region.
Regarding Claim 23, Krogstrup teaches the semiconductor device according to claim 16, wherein the active region is in the form of a nanowire (“SE nanowire” is explicit).
Regarding Claim 24, Krogstrup teaches the semiconductor device according to claim 16, wherein the active region is in the form of a quantum dot.
Regarding Claim 28, Krogstrup teaches a method of fabricating a semiconductor device, the method comprising:
growing a mesa (108) on a surface (top) of a substrate (104) by selective area growth ([059] describes the “SAG phase”), the mesa comprising a semiconductor heterostructure suitable for hosting a 2-dimensional electron gas or a 2-dimensional hole gas ([0064] teaches the 2DEG characteristic); and
subsequently fabricating one or more gate electrodes (112 is formed in P3),
wherein the one or more gate electrodes are configured, when in use, to deplete electrically portions of the semiconductor heterostructure to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from a perimeter of the mesa (essentially the same reasoning as the rejection of claim 16).
Regarding Claims 29, 30, 31, the reasons for rejection have essentially the same citations as claims 17, 18, and 21, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 19, 22, 32, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Krogstrup (WO2019001753 cited in IDS dated 12/08/2023).
Regarding Claim 19, Krogstrup teaches a gated semiconductor structure where the gates define a channel boundary. While Krogstrup may not explicitly recite a 10 nm spacing, the selection of such spacing would have been obvious to a PHOSITA as a routine optimization of the device’s dimensions. The applicant has not alleged unexpected results for this dimensional limitation.
Regarding Claim 22, Krogstrup teaches a semiconductor structure covered by a superconductor. It would have been obvious to a PHOSITA to arrange a gate electrode over said superconductor with an intervening dielectric, as this represents a standard “top-gate” configuration. The inclusion of a gate dielectric is a functional necessity to preventing electrical shorting and enable the field effect, and thus represents a workshop modification rather than an inventive step.
Regarding Claim 32, the same essential citations of claim 22 are also applied to claim 32.
Regarding Claim 35, Krogstrup teaches a gated semiconductor structure. It would have been obvious to a PHOSITA to provide a second layer of gate electrodes separated by gate dielectric, because multi-tier gating is a conventional technique in the art of quantum devices. It can provide independent control over different regions of an active channel. Adding an additional layer is a predictable scaling of the control architecture.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Krogstrup in view of Merckling (EP 3505490 A1, cited in IDS dated 12/08/2023).
Regarding Claim 20, Krogstrup teaches a gated SAG semiconductor device.
Merckling teaches that {1 1 1} crystal orientations are preferred for growing high-quality SU-SE interfaces in quantum devices ([0029], [0035]). It would have bene obvious to a PHOSITA to use the {1 1 1} orientation taught by Merckling in the fabrication of Krogstrup’s device in order to improve the epitaxial quality of the heterostructure.
Claims 24-25 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Krogstrup in view of Ye ("Fabrication and characterization of micromagnet arrays
on top of GaAs/AIGaAs heterostructures", vol. 67, p. 1441-1443, (1995) - XP12013518, cited in IDS dated 12/08/2023).
Regarding Claim 24, Krogstrup teaches a gated SAG structure for defining a nanowire active region, however it does not explicitly teach quantum dots.
However Ye teaches the use of gate-defined dot structures in semiconductor heterostructures (p. 1441, right-hand column, I. 7 - p. 1442, left-hand column, I. 1-5). It would have been obvious to a PHOSITA to adapt the gating geometry of Krogstrup to form a quantum dot instead of a nanowire, as these are the two most common shapes for quantum devices design, and predictable results would be obtained.
Regarding Claim 25, Krogstrup teaches a gated SAG structure for defining a nanowire active region, however it does not explicitly teach ferromagnetic components.
However, Ye teaches integration of ferromagnetic components (e.g. Dysprosium) with semiconductor heterostructures (p. 1442, lefthand column, I. 12-15) for electron modulation. It would have been obvious to a PHOSITA to include such a component in the device of Krogstrup in order to provide a local B-field, which is a normal requirement for topological quantum devices.
Regarding Claim 33, the same essential citations of claim 25 are also applied to claim 33.
Claims 26 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Krogstrup in view of Ye and further in view of Akiro Endo ("Magnetoresistance oscillation in a two-dimensional electron gas under periodic modulation of electric and magnetic fields", Surface Science, vol. 361/362, p. 333-336, (1996) - XP22388200, cited in IDS dated 12/08/2023).
Regarding Claim 26, Krogstrup teaches a gated SAG structure for defining a nanowire active region, however it does not explicitly teach at least one of the one or more gate electrodes is a ferromagnetic component and comprises a ferromagnetic metal.
However Akiro Endo teaches gate electrode comprising a ferromagnetic metal (Nickel) used to modulate a 2DEG. It would have been obvious to a PHOSITA to fabricate a metal electrode from Krogstrup using a ferromagnetic material in order to provide a localized B-field, which can have the effect of lifting spin degeneracy in a quantum device.
Regarding Claim 34, the same essential citations of claim 26 are also applied to claim 34.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Krogstrup in view of Ye and further in view of Winkler (US # 20210126181, cited in IDS dated 12/08/2023).
Regarding Claim 27, Krogstrup teaches a gated SAG structure for defining a nanowire active region, but it does not explicitly teach ferromagnetic component arranged between a conductive gate and the active semiconductor region.
However Winkler teaches a ferromagnetic component arranged between a conductive gate and the active semiconductor region ([0093]-[0094]). It would have been obvious to a PHOSITA to adapt the layering of Winkler to the device of Krogstrup so as to provide a localized B-field, as it helps with spin-splitting in a quantum device.
Conclusion
Citation of pertinent prior art:
US 20200227636 A1
US 20200287120 A1
US 20180166457 A1
US 20200235276 A1
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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