DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/08/2023, 03/21/2024, 04/03/2025 and 01/21/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 9 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Nozawa et al., (WIPO Publication Number WO 2012137949 A1, a machine translation attached to the office action is being used for reference below), hereinafter referenced as Nozawa.
Regarding claim 1, Nozawa teaches a method for manufacturing a power semiconductor device, which comprises forming an active layer on an SiC substrate (Fig.5, active layers, element #14-17, are formed on the SiC substrate, element #12, page 13, paragraph 6, rows 1-4), wherein the forming of the active layer comprises: injecting a source gas onto the SiC substrate (page 8, paragraph 6, rows 3-4); performing a primary purging of injecting a purge gas after stopping the injecting of the source gas (page 8, paragraph 7, rows 1-2); injecting a reactant gas after stopping the primary purging (page 8, paragraph 8, row 3); and performing a secondary purging of injecting the purging gas after stopping the injecting of the reactant gas (page 8, paragraph 9, row 2-3).
Regarding claim 2, Nozawa teaches the method of claim 1 as set forth in the anticipation rejection. Nozawa further teaches the method of claim 1, wherein the source gas comprises one or two or more of Ga, In, Zn, and Si (page 8, paragraph 6, row 7).
Regarding claim 3, Nozawa teaches the method of claims 1 and 2 as set forth in the anticipation rejection. Nozawa further teaches the method of claim 2, wherein the reactant gas comprises one or two or more of As, P, O, and C (page 12, paragraph 2, rows 1-4).
Regarding claim 4, Nozawa teaches the method of claims 1-3 as set forth in the anticipation rejection. Nozawa further teaches the method of claim 3, wherein the forming of the active layer comprises repeatedly performing one process cycle, in which the injecting of the source gas, performing of the primary purging, the injecting of the reactant gas, and the performing of the secondary purging are sequentially performed (page 9, paragraph 1, rows 1-2).
Regarding claim 9, Nozawa teaches the method of claim 1 as set forth in the anticipation rejection. Nozawa further teaches the method of claim 1, wherein injecting the reactant gas comprise generating a plasma by discharging the reactant gas (page 8, paragraph 8, rows 1-4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over LaVoie, (United States Patent Number, US 8,993,460 B2), hereinafter referenced as LaVoie, in view of Ehara, (United States Patent Application Publication Number, US 2009/0239085), hereinafter references as Ehara.
Regarding claim 1, LaVoie teaches a method for manufacturing a power semiconductor device, which comprises forming a SiC active layer on a semiconductor substrate (column 2, rows 31-33). LaVoie does not teach the semiconductor substrate is a SiC substrate. Ehara teaches forming a SiC layer on a SiC substrate (Fig.3, element #105 is a SiC layer, paragraph [0039], row 5 is formed on the substrate #101 which is also SiC, paragraph [0006], rows 1-3). A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the semiconductor substrate disclosed by LaVoie could have been replaced with the SiC substrate disclosed by Ehara because both serve the same purpose of providing substrate that can be used to grow thin film layers of semiconductor devices. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a substrate used to grow thin film layers of semiconductor devices. SiC has higher thermal conductivity and therefore is more suitable for high temperatures applications.
LaVoie further teaches wherein the forming of the active layer comprises: injecting a source gas onto the SiC substrate (column 5, rows 31-32); performing a primary purging of injecting a purge gas after stopping the injecting of the source gas (column 5, rows 35-37, column 9, rows 16-22); injecting a reactant gas after stopping the primary purging (column 5, rows 37-40); and performing a secondary purging of injecting the purging gas after stopping the injecting of the reactant gas (column 5, rows 41-42, column 9, rows 16-22).
Regarding claim 2, the combination of LaVoie and Ehara teaches the method of claim 1 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 1, wherein the source gas comprises one or two or more of Ga, In, Zn, and Si (source gas is contains Si, column 5, rows 32-33).
Regarding claim 3, the combination of LaVoie and Ehara teaches the method of claims 1 and 2 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 2, wherein the reactant gas comprises one or two or more of As, P, O, and C ( reactant gas contains C, column 5, rows 37-40 and column 18, rows 60-65).
Regarding claim 4, the combination of LaVoie and Ehara teaches the method of claims 1, 2 and 3 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 3, wherein the forming of the active layer comprises repeatedly performing one process cycle, in which the injecting of the source gas, performing of the primary purging, the injecting of the reactant gas, and the performing of the secondary purging are sequentially performed (column 5, rows 50-51).
Regarding claim 5, the combination of LaVoie and Ehara teaches the method of claim 1 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 1, wherein the forming of the active layer comprises generating a plasma after the injecting of the reactant gas (column 5, rows 42-45).
Regarding claim 6, the combination of LaVoie and Ehara teaches the method of claims 1 and 5 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 5, wherein the generating of the plasma after the injecting of the reactant gas is performed after the performing of the secondary purging (column 5, rows 42-45), and the forming of the active layer comprises repeatedly performing one process cycle, in which the injecting of the source gas, the performing of the primary purging, the injecting of the reactant gas, the performing of the secondary purging, and the generating of the plasma are sequentially performed (column 5, rows 50-51).
Regarding claim 8, the combination of LaVoie and Ehara teaches the method of claims 1 and 5 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 5, wherein the generating of the plasma comprises injecting a hydrogen gas (column 10, rows 40-45).
Regarding claim 9, the combination of LaVoie and Ehara teaches the method of claim 1 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 1, wherein injecting the reactant gas comprise generating a plasma by discharging the reactant gas (column 10, rows 10-14).
Regarding claim 10, the combination of LaVoie and Ehara teaches the method of claims 1 and 9 as set forth in the obviousness rejection. LaVoie further teaches the method of claim 9, wherein the forming of the active layer comprises generating a plasma after the injecting of the reactant gas (Fig.1, plasma is generating after the reactant is injected).
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over LaVoie in view Ehara and in view of Okuda, (United States Patent Application Publication Number, US 2015/0101533 A1) hereinafter referenced as Okuda.
Regarding claim 7, the combination of LaVoie and Ehara teaches the method of claim 1 as set forth in the obviousness rejection. The combination of LaVoie and Ehara does not teach the method of claim 1, wherein the forming of the active layer comprises generating a plasma between the injecting of the source gas and the injecting of the reactant gas. Okuda teaches wherein the forming of the active layer comprises generating a plasma between the injecting of the source gas and the injecting of the reactant gas (Fig.11, plasma is generated between injecting of the source gas, and injecting of the reactant gas). We note that both LaVoie and Okuda disclose a source gas containing dichlorosilane, that results in the formation of silicon containing layer on the substrate (LaVoie, column 19, rows 29-31, and Okuda, paragraph [0068], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Okuda and disclose the forming of the active layer comprises generating a plasma between the injecting of the source gas and the injecting of the reactant gas. As disclose by Okuda, the plasma generated between the injecting of the source gas and the injecting of the reactant gas is used to create a high quality Si containing layer by desorbing impurities from the layer (paragraph [0132], rows 5-9).
Regarding claim 15, the combination of LaVoie and Ehara teaches the method of claims 1 and 9 as set forth in the obviousness rejection. The combination of LaVoie and Ehara does not teach the method of claim 9, wherein the forming of the active layer comprises generating a plasma between the injecting of the source gas and the injecting of the reactant gas. Okuda teaches wherein the forming of the active layer comprises generating a plasma between the injecting of the source gas and the injecting of the reactant gas (Fig.11, plasma is generated between injecting of the source gas, and injecting of the reactant gas). We note that both LaVoie and Okuda disclose a source gas containing dichlorosilane, that results in the formation of silicon containing layer on the substrate (LaVoie, column 19, rows 29-31, and Okuda, paragraph [0068], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Okuda and disclose the forming of the active layer comprises generating a plasma between the injecting of the source gas and the injecting of the reactant gas. As disclosed by Okuda, the plasma generated between the injecting of the source gas and the injecting of the reactant gas is used to create a high quality Si containing layer by desorbing impurities from the layer (paragraph [0132], rows 5-9).
Claims 1, 11, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al., (United States Patent Number, US 6534801 B2) hereinafter referenced as Yoshida, in view of Nozawa.
Regarding claim 1, Yoshida teaches a method for manufacturing a power semiconductor device (Fig.1 to 5), which comprises forming an active layer (Fig.2, element #3) on a sapphire substrate (Fig.2, element #1). Yoshida does not teach the substrate is a SiC substrate. Nozawa teaches forming a layer of the same material as Yoshida (Fig.5, element #14 is GaN) on a SiC substrate(Fgi.5, substrate, element #12, page 13, paragraph 6, rows 1-4). Thus, both references Yoshida and Nozawa teach a substrate used to grow GaN layers. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the sapphire substrate disclosed by Yoshida could have been replaced for the SiC substrate disclosed by Nozawa because both serve the same purpose of providing substrate that can be used to grow GaN. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a substrate used to grow GaN. SiC has higher thermal conductivity and therefore is more suitable for high temperatures applications.
Yoshida teaches forming the active layer using MOCVD and/or MBE methods (column 3 rows 1-3). Yoshida does not teach wherein the forming of the active layer comprises: injecting a source gas onto the SiC substrate; performing a primary purging of injecting a purge gas after stopping the injecting of the source gas; injecting a reactant gas after stopping the primary purging; and performing a secondary purging of injecting the purging gas after stopping the injecting of the reactant gas. Nozawa teaches wherein the forming of the active layer comprises: injecting a source gas onto the SiC substrate (page 8, paragraph 6, rows 3-4); performing a primary purging of injecting a purge gas after stopping the injecting of the source gas (page 8, paragraph 7, rows 1-2); injecting a reactant gas after stopping the primary purging (page 8, paragraph 8, row 3); and performing a secondary purging of injecting the purging gas after stopping the injecting of the reactant gas (page 8, paragraph 9, row 2-3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nozawa and disclose forming of the active layer comprises: injecting a source gas onto the SiC substrate; performing a primary purging of injecting a purge gas after stopping the injecting of the source gas; injecting a reactant gas after stopping the primary purging; and performing a secondary purging of injecting the purging gas after stopping the injecting of the reactant gas. As disclosed by Nozawa, this process can produce high quality GaN layers at low temperature, while reducing the warping and distortion due to the difference in thermal expansion coefficient of different layers that form the structure (page 2, paragraph 6, rows 3-6).
Regarding claim 11, the combination of Yoshida and Nozawa teaches the method of claim 1 as set forth in the obviousness rejection. Yoshida further teaches forming a well region in the active layer after the forming of the active layer (Fig.5, well regions element #5 are formed in the active layer, element #3, after the formation of element #3) wherein the forming of the well region comprises: exposing a partial area of the active layer in which the well region is formed (Fig.3, portions of element #3 are exposed from element #6 and exposed once layer element #4 is etched); etching the exposed partial area of the active layer (Fig.4, exposed portions of element #3 are etched). Yoshida teaches forming the well of GaN material, by using a selective growth that requires Ga, ammonia as an N source, to form the well region in the exposed area of the active layer (column 5, rows 9-15). However, Yoshida does not teach the process steps of forming the GaN layer. Nozawa teaches forming a GaN layer using a process that sequentially performs the injecting of the source gas (page 8, paragraph 6, rows 3-4), the injecting of the purge gas (page 8, paragraph 7, rows 1-2), the injecting of the reactant gas (page 8, paragraph 8, row 3), and the injecting of the purge gas (page 8, paragraph 9, row 2-3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nozawa and disclose sequentially performing the injecting of the source gas, the injecting of the purge gas, the injecting of the reactant gas, and the injecting of the purge gas to form the well region in the exposed area of the active layer to form the well region. As disclosed by Nozawa, this process can produce high quality GaN layers at low temperature, while reducing the warping and distortion due to the difference in thermal expansion coefficient of different layers that form the structure (page 2, paragraph 6, rows 3-6).
Regarding claim 12, the combination of Yoshida and Nozawa teaches the method of claims 1 and 11 as set forth in the obviousness rejection. Yoshida does not teach the method of claim 11, wherein at least one of the forming of the active layer and the forming of the well region comprises injecting a doping gas, wherein the doping gas is injected after the doping gas is mixed with the source gas and is injected or after the source gas is injected. Nozawa teaches the method of claim 11, forming of an active layer comprises injecting a doping gas, wherein the doping gas is injected after the doping gas is mixed with the source gas and is injected (column 8, paragraph 2, rows 3-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Nozawa and disclose forming of an active layer comprises injecting a doping gas, wherein the doping gas is injected after the doping gas is mixed with the source gas and is injected. As disclosed by Nozawa, this process makes it possible to form a GaN layer having good crystallinity at low temperature, without supplying a predetermined bias.
Regarding claim 13, the combination of Yoshida and Nozawa teaches the method of claims 1, 11 and 12 as set forth in the obviousness rejection. Nozawa further teaches the method of claim 12, wherein the doping gas comprises one of Mg, Si, In, Al, and Zn (the doping gas comprises Si, page 8, paragraph 2, rows 6-7).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Nozawa, and in view of Zhang et al., (United States Patent Application Publication Number, US 2020/0373383 A1) hereinafter referenced as Zhang.
Regarding claim 14, the combination of Yoshida and Nozawa teaches the method of claim 11 as set forth in the obviousness rejection. Yoshida further teaches the method of claim 11, further comprising: forming an insulating layer on the active layer (column 4, rows 22-27); forming a source electrode and a drain electrode on the well region so that the source electrode and the drain electrode are spaced apart from each other in a horizontal direction (Fig.1, source electrode, element #S and drain electrode, element #D, are formed and spaced apart), and forming a gate electrode (Fig.1, gate electrode, element #G is formed).
Yoshida teaches forming a gate electrode on an undoped AlGaN layer. Yoshida does not teach forming a gate insulating layer and a gate electrode on the gate insulating layer. Zhang teaches a gate insulating layer and a gate electrode on the gate insulating layer (Fig.1C shows the gate on the gate insulator layer). Both references Yoshida and Zhang disclose high electron mobility transistors made of GaN /AlGaN materials. Zhang discloses several versions of the high mobility transistors: in Fig.1A, the gate is in contact with an AlGaN material, similar to Yoshida’s disclosure, while in Fig1C, the AlGaN layer which is in contact with the gate in Fig.1A, is replaced by an insulator. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Zhang and disclose a gate electrode on the gate insulating layer. As disclosed by Zang, the insulator results in the introduction of negative charges under the gate, which allows a reduction in the electron density under the gate (paragraph [0018], rows 22-24), which has the benefit of reducing the breakdown voltage.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899