DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11 February 2026, 06 March 2026 and 03 April 2026 were filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Terminal Disclaimer
The terminal disclaimer filed on 06 March 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of Application Number 18/260,468 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Amendment
Amendment filed on 06 March 2026 has been entered. Claims 1-20 are now pending in the application.
Amendments to the claim 8 to overcome the rejections under U.S.C 112(b) have been fully considered and the rejection under 35 U.S.C. 112(b) of claim 8 has been withdrawn.
Response to Arguments
Applicant’s arguments, see Page 8, filed 06 March 2026, with respect to the rejection(s) of claim(s) 1-5 and 7-10 under 5 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yoshida.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-10 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto (WO 2017094470, see US 20200337156 for English Translation) in view of Yoshida (US 20160050769).
Regarding claim 1, Matsumoto teaches, a method for manufacturing a wiring board (printed circuit board 101, Figs. 1A to 1L, para, [0020]), the method comprising steps of:
(I) forming an insulation material layer (first insulating resin layer 3, alternatively, primer layer 4, see annotated Fig. 1A below) on a surface of a support substrate (insulating substrate 1, Fig. 1A to 1L);
(II) forming a first conductive layer (copper layer 5, Fig. 1B) on a surface of the insulation material layer by electroless copper plating (copper layer 5…formed by electroless plating, para. [0025]);
[AltContent: arrow][AltContent: textbox (first conductive layer)][AltContent: textbox (resist pattern)][AltContent: ][AltContent: textbox (second conductive layer)][AltContent: arrow][AltContent: textbox (insulating layer)][AltContent: arrow][AltContent: textbox (support substrate)][AltContent: ][AltContent: textbox (second opening)][AltContent: arrow][AltContent: textbox (first opening)][AltContent: ]
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Annotated Figs. 1A to 1G, Matsumoto.
(III) forming a first opening (via hole 6, Fig. 1C) passing through the first conductive layer and the insulation material layer (see the via hole 6, via holes 6 are formed such as by laser irradiation, penetrating the copper layer 5, the primer layer 4, and the first insulating resin layer 3, para. [0027]);
(IV) forming a second conductive layer (copper plated layer 9, Fig. 1F) on a bottom surface and a side surface of the first opening by electroless copper plating (an electroless copper plated layer 9 is formed by electroless plating to cover the bottom surfaces of the via holes 6, the sidewall surfaces thereof, para. [0032]);
(V) forming a resist pattern (resist pattern 10, Fig. 1G) having a second opening (see the opening in annotated Fig. 1G) communicating with the first opening on a surface of the second conductive layer (see the openings, Fig. 1G); and
(VI) filling the first opening and the second opening with a conductive material (a copper electroplated layer 11, Fig. 1H) including copper by electrolytic copper plating (a copper electroplated layer 11 is formed by copper electroplating on the copper electroless-plated layer 9 on which the resist pattern 10 is formed, Fig. 1H, para. [0034], electroplating is an electrolytic plating process).
Matsumoto does not teach forming a second conductive layer on a surface of the first conductive layer. However, Yoshida teaches a method for manufacturing a wiring board in Fig. 2, including forming an insulation material layer (prepreg 3, Fig. 2, step 2-1) on a surface of a support substrate (2); forming a first conductive layer (copper foil 4 and electroless copper plating layer 6) on a surface of the insulation material layer; forming a second conductive layer (electrolytic filled copper plating layer 7, Fig. 2, step 2-2) on a surface of the first conductive layer (electroless copper plating layer 6) and on a bottom surface and a side surface of the first opening by electroless copper plating; and forming a resist pattern (resist 11). Matsumoto teaches an electroless copper plated layer 9 (see the Note below). Yoshida teaches forming copper plating layer 7 on the surface of an electroless copper plating layer 6. Therefore, in view of the teachings of Yoshida, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing a wiring board of Matsumoto and to include an electroless copper plating layer 6 as taught by Yoshida in Fig. 2, step 2-2 so that it enables forming a second conductive layer on a surface of the first conductive layer. Doing so would enable forming a desired thickness of the conducting layer and removing any additive and foreign matters on the surface of the first conductive layer as Yoshida disclosed in para. [0040]. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in forming an electroless copper second conductive layer on a surface of the electroless copper first conductive layer. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Note: Though, Yoshida teaches in para. [0060], removing the first conductive layer, which results in a similar structure at the opening as applicant disclosed in step (III). See, claim 1, lines 6-7, “(III) forming a first opening passing through the first conductive layer and the insulation material layer”, in which it is obvious that the first opening removes the first conducting layer at the opening.
Regarding claim 2, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the method according to claim 1, wherein a thickness of the first conductive layer is 20 to 590 nm (copper layer 5 preferably has a thickness of 3 μm or less, para. [0026]).
Regarding claim 3, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the method according to claim 1, wherein a thickness of the first conductive layer is 210 to 590 nm (copper layer 5 preferably has a thickness of 3 μm or less, para. [0026]).
Regarding claim 4, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the method according to claim 1, wherein in the step (III), the first opening is formed with a carbon dioxide laser (via holes 6 are formed such as by laser irradiation,…various lasers can be used for this laser irradiation, including a carbon dioxide laser, para. [0027-0028]).
Regarding claim 5, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the method according to claim 1, wherein the resist pattern in the step (V) further has a plurality of grooves (see the groove in annotated Fig. 1G below) which extend to the surface of the second conductive layer and are provided in parallel, and in the step (VI), the plurality of grooves are also filled with a conductive material including copper by electrolytic copper plating to form a wiring (see Figs. 1H to 1L, a copper electroplated layer 11 is formed by copper electroplating on the copper electroless-plated layer 9 on which the resist pattern 10 is formed, para. [0034]).
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Annotated Figs. 1G and 1H, Matsumoto.
Regarding claim 7, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the method according to claim 1, further comprising steps of: (VII) peeling the resist pattern (a ninth step of peeling the resist pattern, para. [0010]); and (VIII) removing the second conductive layer exposed due to peeling of the resist pattern, and the first conductive layer that is in contact with the exposed second conductive layer (a tenth step of removing the copper electroless-plated layer in regions empty of the resist pattern, following the ninth step, para. [0010]).
[AltContent: arrow][AltContent: textbox (additional insulation layer)]
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Annotated Fig. 1L, Matsumoto.
Regarding claim 8, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 7. Matsumoto further teaches, the method according to claim 7, wherein a multi-layered wiring layer is formed on the support substrate through steps of: (IX) further forming an additional insulation material layer (second insulating layer 15, see annotated Fig. 1L) to cover a wiring provided on the insulation material layer after the step (VIII), and (X) repeating the steps (II) to (IX) one or more times after performing step (IX) (see Fig. 5A, more than one wiring layer 12, para. [0140]).
Regarding claim 9, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the wiring board manufactured by the method according to claim 1, comprising: the support substrate (insulating substrate 1, Fig. 1A to 1L); the insulation material layer provided on the surface of the support substrate (first insulating resin layer 3, alternatively, primer layer 4, see annotated Fig. 1A above); and the first conductive layer provided on the surface of the insulation material layer in a thickness of 20 to 590 nm (copper layer 5 preferably has a thickness of 3 μm or less, para. [0026]).
Regarding claim 10, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the wiring board according to claim 9, wherein the thickness of the first conductive layer is 210 to 590 nm (copper layer 5 preferably has a thickness of 3 μm or less, para. [0026]).
Regarding claim 15, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the method according to claim 1, wherein the first conductive layer has an upper surface that is exposed during the step (III) of forming the first opening (see Fig. 1B). Yoshida further teaches, the second conductive layer is formed on the upper surface of the first conductive layer at the step (IV) (see step 2-2, Fig. 2). Therefore, in view of the teachings of Yoshida, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method for manufacturing a wiring board of Matsumoto and to include an electroless copper plating layer 6 as taught by Yoshida in Fig. 2, step 2-2 so that it enables forming a desired thickness of the conductive layer.
Regarding claim 16, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the wiring board manufactured by the method according to claim 15, comprising: the support substrate (insulating substrate 1); the insulation material layer (first insulating resin layer 3, alternatively, primer layer 4) provided on the surface of the support substrate; the first conductive layer (copper layer 5, Fig. 1B) provided on the surface of the insulation material layer. Yoshida further teaches, the second conductive layer provided on the surface of the first conductive layer (see step 2-2, Fig. 2). Please also refer to the rationale for combination regarding claim 1, as it is applicable to claim 16 in the same manner.
Regarding claim 17, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the wiring board according to claim 16, wherein the first conductive layer has a thickness of 20 to 590 nm (copper layer 5 preferably has a thickness of 3 μm or less, para. [0057]).
Regarding claim 18, Matsumoto in view of Yoshida teaches the recited limitations with respect to claim 1. Matsumoto further teaches, the wiring board according to claim 16, wherein the first conductive layer has a thickness of 210 to 590 nm (copper layer 5 preferably has a thickness of 3 μm or less, para. [0057]).
Claim(s) 6, 11-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Yoshida as applied to claim 1 above, and further in view of Masaya (JP 2019091840).
Regarding claim 6, modified Matsumoto does not teach, a width of each of the grooves is 1 to 100 µm, and an interval between two adjacent grooves is 1 to 100 µm. However, Masaya teaches a method of manufacturing a wiring board including forming a first conductive layer 10 on a surface of the insulation material layer 1; forming a first opening; forming a second conductive layer; forming a resist pattern; and filling the first opening and the second opening with a conductive material including copper in which, the method according to claim 5, wherein a width of each of the grooves is 1 to 100 µm, and an interval between two adjacent grooves is 1 to 100 µm (forming a resist pattern 6 having a groove with a line width of 0.5 to 20 μm on the surface of the insulating material layer 2, the wiring layer having a wiring with a fine trench structure is formed. It can be manufactured. The space width of the openings 6a is also preferably in the range of 0.5 to 20 μm, para. [0024]). Therefore, in view of the teachings of Masaya, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of a wiring board of Matsumoto and to limit the width of the grooves so that it enables forming wiring patterns having a desired trench structure.
Regarding claims 11, 13 and 19, modified Matsumoto does not teach, the support substrate comprises a prepreg including cloth; and a copper layer formed on a surface of the prepreg. However, Masaya further teaches, wherein the support substrate comprises: a prepreg including cloth (support substrate 1 is…, a wiring board containing glass cloth,…sealing resin, para. [0029], see the specification para. [0027]); and a copper layer (copper layer 1a, Fig. 1) formed on a surface of the prepreg (Fig. 1, supporting substrate 1 shown in the figure has a copper layer 1a formed on its surface, para. [0028, 0067]]). Therefore, in view of the teachings of Masaya, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of a wiring board of Matsumoto and to replace the insulating substrate 1 of Matsumoto with a support substrate 1 as Masaya taught in Fig. 1 so that it enables forming wiring patterns having wiring pads as Masaya disclosed in para. [0028].
Regarding claims 12, 14 and 20, Masaya further teaches, wherein the insulation material layer is a prepreg including cloth (support substrate 1 is…, a wiring board containing glass cloth, a semiconductor element containing sealing resin, para. [0029]). Please also refer to the rationale for combination regarding claim 13, as it is applicable to claim 14 in the same manner.
Conclusion
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
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