DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 7/8/2026. Claims 1 & 4-9 are pending in this application. Claims 2-3 are canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1, 4-6, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Takeuchi et al. (US 2020/0395329).
Re claim 1, Takeuchi teaches, under BRI, Figs. 2-4, [0019, 0022, 0030, 0031, 0033, 0037], a semiconductor module comprising:
-a plurality of base plates (plates 30) made of conductive members (e.g., copper) and formed in plate shapes (Fig. 2);
-at least one semiconductor element (switching element 10a, 12a) joined to a one-surface side of at least one of the base plates (30); and
-at least one connection member (wiring member 4A, 4B) made of a conductive member and connecting one-surface sides of two or more of the base plates (30), wherein
the plurality of base plates (30) are arranged with gaps therebetween on the same plane (Fig. 3), and
the connection member (4A, 4B) has one or both of a semiconductor element connection portion (e.g., through hole 45 at element connection portion 42) which is a part connected to the base plate (30) via the semiconductor element (10a, 12a), and a base plate connection portion (e.g., through hole 45 at plate connection portion 43) which is a part directly connected to the base plate (30) (Fig. 3),
wherein
the connection member (4A, B) has, at a part (portion 41) connected between the two base plates (two adjacent plates 30), a flat portion (upper portion of 41, indicated) which is spaced apart from the one-surface of the base plate (left or right plate 30) and whose surface on a side opposite to the base plate side is parallel to the one-surface of the base plate (30),
the connection member (4A, B) is formed in a plate shape, and
a width of the flat portion (upper portion of 41, indicated) is greater than a width of the semiconductor element connection portion (e.g. through hole 45 at portion 42) and a width of the base plate connection portion (e.g., through hole 45 at portion 43).
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Re claim 5, Takeuchi teaches, Fig. 3, [0033], the connection member (4A, B) has, at respective centers of the semiconductor element connection portion and the base plate connection portion, through holes (45) penetrating in normal directions of the one-surfaces of the base plates (30).
Re claim 6, Takeuchi teaches, under BRI, Figs. 2-3, a plurality of the through holes (45) are provided so as to be arranged in one direction (e.g., vertical), the connection member (4A, B) extends in the direction in which the plurality of through holes are arranged, and as seen in a direction perpendicular to the one-surfaces of the base plates (30), the connection member (4A, B) is formed to be line-symmetric with respect to a line connecting respective centers of the plurality of through holes (45).
Re claim 9, Takeuchi teaches, Fig. 4, a surface of the connection member (4A, B) on a side opposite to the base plate side (of 30) is parallel to the one-surfaces of the base plates (30), and connection portions (at portion 43) of the connection member (4B) with the base plates (30) protrude toward the base plate side (of 30).
Re claim 4, Takeuchi teaches, under BRI, Figs. 2-4, [0019, 0022, 0030, 0031, 0033, 0037], a semiconductor module comprising:
-a plurality of base plates (plates 30) made of conductive members (e.g., copper) and formed in plate shapes (Fig. 2);
-at least one semiconductor element (switching element 10a, 12a) joined to a one-surface side of at least one of the base plates (30); and
-at least one connection member (wiring member 4A, 4B) made of a conductive member and connecting one-surface sides of two or more of the base plates (30), wherein
the plurality of base plates (30) are arranged with gaps therebetween on the same plane (Fig. 3), and
the connection member (4A, 4B) has one or both of a semiconductor element connection portion (e.g., through hole 45 at element connection portion 42) which is a part connected to the base plate (30) via the semiconductor element (10a, 12a), and a base plate connection portion (e.g., through hole 45 at plate connection portion 43) which is a part directly connected to the base plate (30) (Fig. 3),
wherein
the connection member (4A, B) has, at a part (portion 41) connected between the two base plates (two adjacent plates 30), a flat portion (upper portion of 41) which is spaced apart from the one-surface of the base plate (left or right plate 30) and whose surface on a side opposite to the base plate side is parallel to the one-surface of the base plate (30),
the connection member (4A, B) has at least two said flat portions (portions at 41 & 42), and
heights from the one-surfaces of the base plates (30) to the two flat portions (portions at 41 & 42) are different from each other (e.g., 41 is higher than 42).
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Re claim 8, Takeuchi teaches, under BRI, Figs. 2-4, [0019, 0022, 0030, 0031, 0033, 0037], a semiconductor module comprising:
-a plurality of base plates (plates 30) made of conductive members (e.g., copper) and formed in plate shapes (Fig. 2);
-at least one semiconductor element (switching element 10a, 12a) joined to a one-surface side of at least one of the base plates (30); and
-at least one connection member (wiring member 4A, 4B) made of a conductive member and connecting one-surface sides of two or more of the base plates (30), wherein
the plurality of base plates (30) are arranged with gaps therebetween on the same plane (Fig. 3), and
the connection member (4A, 4B) has one or both of a semiconductor element connection portion (e.g., through hole 45 at element connection portion 42) which is a part connected to the base plate (30) via the semiconductor element (10a, 12a), and a base plate connection portion (e.g., through hole 45 at plate connection portion 43) which is a part directly connected to the base plate (30) (Fig. 3),
mold resin sealing (7) the plurality of base plates (30), the semiconductor element (10a, 12a), and the connection member (4A, B), wherein
as seen in a direction perpendicular to the one-surfaces of the base plates (30) an outer shape of the mold resin (7) is a rectangular shape having long sides and short sides, and
the connection member (4A, B) extends in a direction parallel to the long-side direction of the mold resin (7).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi.
The teachings of Takeuchi have been discussed above.
Re claim 7, Takeuchi teaches Fig. 2, a plurality of the through holes (45) are provided so as to be arranged in one direction (e.g., vertical), the connection member (4A, B) extends in the direction in which the plurality of through holes are arranged.
Takeuchi’s Fig. 2 does not explicitly teach as seen in a direction perpendicular to the one-surfaces of the base plates, the connection member is formed to be line-asymmetric with respect to a line connecting respective centers of the plurality of through holes.
Takeuchi’s Fig. 6 teaches, [0047], as seen in a direction perpendicular to the one-surfaces of the base plates (30), the connection member (wiring member 5C) is formed to be line-asymmetric with respect to a line connecting respective centers of the plurality of through holes (45).
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Takeuchi’s Fig. 6 to achieve the connection member is formed to be line-asymmetric with respect to a line connecting respective centers of the plurality of through holes as claimed, because a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Response to Arguments
4. Applicant's arguments filed 7/8/2026 have been fully considered but they are not persuasive.
Applicant submits “as shown in Fig. 3, no flat portion has width greater than a width of a semiconductor connection portion. As is apparent from Fig. 3, the width is equal to or less than the semiconductor element connection portion”.
The examiner respectfully disagrees.
Shown in Figs. 3-4, and indicated Fig. 3, Takeuchi teaches a width (left to right) of the flat portion (upper portion of 41, indicated) is greater than a width of the semiconductor element connection portion (e.g. through hole 45 at portion 42). Top surface of 41 considered as flat portion, and it is clearly, width of 41 is larger than width of through hole 45. There is not clear response & support in the remark, that “the width is equal to or less than the semiconductor element connection portion”.
Applicant submits “as is clear from Fig. 3, the flat portions 41 are all equal height from the one-surfaces of the base plate 30”.
The examiner respectfully disagrees.
The previous/current rejections each indicate 2 flat portions (portions at 41, 42). It is clear that they are at two different levels from surface of 30 (indicated in Fig. 3). Hence, Takeuchi teaches flat portions (at 41, 42) are different heights (in vertical direction) from the base plate 30.
Applicant submits “In Fig. 2, the connection (wire members) extends perpendicular to the long side direction of the mold resin- not parallel.”
The examiner respectfully disagrees.
In view of Figs. 3-4 of Takeuchi, mold resin (7) has long (x axis) and short (y axis) sides. Each wiring member (4A, 4B) extends parallel with the long side of the mold resin (7). Even in top view of Fig. 2, each wiring member (4A, B) has length and width, the widths of 4A, 4B extend in parallel with long side of the mold resin (7).
A result, given a broadest reasonable interpretation, Takeuchi meets the claimed invention.
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fujita et al. (US 2013/0221532, Figs. 1 & 4) discloses a semiconductor module includes upper/lower arm switching elements integrated to a high-potential/load conductor.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/5/26
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