Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 16-22) in the reply filed on 05/14/2026 is acknowledged.
Claims 23-30 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/14/2026.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “terminal region and the p-type ring” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 line 5 recites the limitation "the junction depth". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimoto et al. (US 2021/0083099).
As for claim 16, Kimoto et al. disclose in Fig. 1 and the related text a super junction device, wherein a device unit region of the super junction device comprises:
a super junction composed of P-type pillars 32 and N-type pillars 26 arranged alternately, one of the P- type pillars 32 and an adjacent N-type pillar 26 forming a super junction unit (Fig. 1);
the P-type pillar 32 is formed by a P-type epitaxial layer filling a super junction trench (Fig. 1), the N-type pillar 26 is formed by a first N-type epitaxial layer located between the P-type pillars (Fig. 1), and the super junction trench is formed in the first N-type epitaxial layer 26 (Fig. 1);
a P-type body region 28 is formed in the first N-type epitaxial layer 26;
each super junction device unit further comprises a gate structure 16/18, the gate structure being a trench gate 16 comprising a gate trench 21, a gate dielectric layer 18 formed on the inner surface of the gate trench 21, and a polysilicon gate 16 filling the gate trench 21 [0062];
at least one side surface of the gate trench 21 is located in the N-type pillar 26, and the depth of the gate trench 21 is greater than the junction depth of the P-type body region 28 (Fig. 1);
the top surface of the gate trench 21 is level with the top surface of the super junction unit (fig. 1), and the top surface of the polysilicon gate 16 is “etched back” (see below) below the top surface of the gate trench (Fig. 1);
a source region 30 is formed by an N+ doped region (Fig. 1) “which is formed by performing ion implantation on the side surface of the gate trench on the top of the polysilicon gate and on the surface of the P- type body region outside the gate trench” (see below); and
the surface of the P-type body region 28 at the bottom of the source region 30 and covered by the side surface of the polysilicon gate 16 is used to form a channel (Fig. 1), the length of the channel is controlled by controlling the position of the top surface of the polysilicon gate so as to control gate-source capacitance, and a larger distance between the top surface of the polysilicon gate and the top surface of the gate trench corresponds to a shorter channel and smaller gate-source capacitance (Fig. 1, Kimoto et al. teach in same structure as claimed invention therefore it is capable to have the length of the channel is controlled by controlling the position of the top surface of the polysilicon gate so as to control gate-source capacitance, and a larger distance between the top surface of the polysilicon gate and the top surface of the gate trench corresponds to a shorter channel and smaller gate-source capacitance).
The recited limitations “etch back”, “formed by performing ion implantation on the side surface of the gate trench on the top of the polysilicon gate and on the surface of the P- type body region outside the gate trench” are drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113.
As for claim 17, Kimoto et al. disclose the super junction device according to claim 16, wherein the P-type body region is formed by superimposing a first P-type doped region and a second P-type doped region, so as to increase the junction depth of the P-type body region; the first P-type doped region is formed by means of ion implantation and annealing drive-in before the P-type pillar is formed, the doping concentration and depth of the first P-type doped region are determined by corresponding ion implantation and annealing drive-in processes, and the annealing drive-in process of the first P-type doped region is not limited by process conditions of the super junction comprising the P-type pillar such that the depth of the first P-type doped region can be increased, thereby increasing the junction depth of the P-type body region; and before the polysilicon gate is etched back, under the condition that the top surface of the polysilicon gate is level with the top surface of the gate trench, the second P-type doped region is formed in the first P-type doped region on two sides of the gate structure by means of full ion implantation in a self-aligned manner, the full ion implantation for forming the second P-type doped region being used to adjust a threshold voltage for forming the channel.
Claim 17 is drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113.
As for claim 21, Kimoto et al. disclose the super junction device according to claim 16, wherein an N+ doped drain region 24 is formed at the bottom of the first N-type epitaxial layer 26.
The limitation of “the drain region is formed by the thinned N+ doped semiconductor substrate or formed by performing N+ back ion implantation on the thinned semiconductor substrate” is drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113.
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 18-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kimoto et al. (US 2021/0083099).
As for claims 18 and 22, Kimoto et al. disclose the super junction device according to claim 17, wherein a terminal region (one of outer 32) of the super junction device is formed on the periphery of the device unit region, and the terminal region comprises a P-type ring surrounding (portion of) the device unit region, the first P-type doped region and the P-type ring have the same doped structure (Fig. 1).
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the junction depth is 1-5 micrometers; and the junction depth of the P-type body region is 3 micrometers, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The limitation of “…are simultaneously formed by means of the same ion implantation and annealing drive-in processes”; and “an implantation dose of the ion implantation for forming the first P-type doped region is greater than 2e13 cm-2” is drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113.
As for claim 19, Kimoto et al. disclose the super junction device according to claim 18, wherein the first N-type epitaxial layer 26 is formed on the surface of a semiconductor substrate lower portion of 26/24 (Fig. 1).
As for claim 20, Kimoto et al. disclose the super junction device according to claim 19, wherein the semiconductor substrate (lower portion of 26) is a silicon substrate [0043], the first N-type epitaxial layer (upper portion of 26) is a silicon epitaxial layer [0043], and the P-type epitaxial layer 28 of the P-type pillar is a silicon epitaxial layer [0043].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG Q TRAN/Primary Examiner, Art Unit 2811
Prosecution Insights