Prosecution Insights
Last updated: April 19, 2026
Application No. 18/569,679

SEMICONDUCTOR MODULE

Non-Final OA §102
Filed
Dec 13, 2023
Examiner
HO, ANTHONY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Power Semiconductor Device, Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1007 granted / 1110 resolved
+22.7% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
38 currently pending
Career history
1148
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
31.8%
-8.2% vs TC avg
§102
40.5%
+0.5% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1110 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on December 13, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eiji et al (JP 2004-221516). In re claim 1, Eiji et al discloses a semiconductor module comprising: an insulating substrate (i.e. 23); a wiring (i.e. 22) formed on the insulating substrate; a semiconductor chip (i.e. 30); and a lead frame (i.e. 40), wherein the semiconductor chip has one surface connected to the wiring and another surface connected to the lead frame, the wiring includes a floating wiring (i.e. 2231, 2232) to which the lead frame is connected, and a connection point between the floating wiring and the lead frame is located at a corner part of the insulating substrate (i.e. see at least Figures 1, 2, and 7 and paragraphs 0043-0045 and 0065). In re claim 2, Eiji et al discloses wherein the connection point between the floating wiring and the lead frame is located on a further outer peripheral side of the insulating substrate than another connection point between the lead frame and the wiring (i.e. see at least Figures 1, 2, and 7). In re claim 3, Eiji et al discloses wherein the insulating substrate is formed of ceramics (i.e. paragraph 0043 discloses the substrate is a ceramic substrate), and the lead frame is formed of copper (i.e. see at least paragraph 0045). In re claim 5, Eiji et al discloses further comprising a heat dissipation member (i.e. 10) on a surface on a side of the insulating substrate opposite to the semiconductor chip, wherein the heat dissipation member is disposed to overlap the floating wiring with the insulating substrate interposed between the heat dissipation member and the floating wiring (i.e. see at least Figures 1, 2, and 7). Allowable Subject Matter Claims 4 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 13, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604478
SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12593662
ELECTRONIC DEVICE FOR DETECTING DEFECT IN SEMICONDUCTOR PACKAGE AND OPERATING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12575309
PRODUCTION METHOD FOR PATTERNED ORGANIC FILM, PRODUCTION APPARATUS FOR PATTERNED ORGANIC FILM, ORGANIC SEMICONDUCTOR DEVICE PRODUCED BY SAME, AND INTEGRATED CIRCUIT INCLUDING ORGANIC SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 10, 2026
Patent 12575267
DISPLAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS
2y 5m to grant Granted Mar 10, 2026
Patent 12568758
LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.3%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1110 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month