DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 14, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19, 25, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al (CN 108922920) in view of Wang et al (CN 210866178) and Zhang et al (CN 206340551).
In re claim 19, Jiang et al discloses a unidirectional transient voltage suppression diode, comprising: a substrate (i.e. 10) of a first conductivity type (i.e. in this case, p-type), and a first implantation region (i.e. one of the 30) and a second implantation region (i.e. the other 30) of a second conductivity type (i.e. in this case, n-type); wherein the first implantation region is disposed on a front side of the substrate, the second implantation region is disposed on a back side of the substrate (i.e. see at least Figure 6), and a barrier layer (i.e. 40) on a front surface of the substrate from the bottom up; first metal (i.e. 50) is led out of the first implantation region as a first electrode, and second metal (i.e. 60) is led out of the second implantation region on the back side and the substrate respectively as a second electrode, so that the second implantation region on the back side of the substrate is short-circuited with the substrate (i.e. see at least Figure 7); and the first conductivity type is different from the second conductivity type (i.e. in this case, p-type and n-type are different).
Jiang et al does not explicitly disclose the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate; an insulation layer with the barrier layer arranged in sequence on a front surface of the substrate from the bottom up; the insulation layer is disposed between the barrier layer and a first metal layer.
However, Wang et al discloses the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate (i.e. see at least Figure 1 showing P+1 region is located on the front surface of the substrate 4, the P+2 region is located on the back surface of the substrate, and the junction depth of the pn junction between the P+2 region and an N region is less than the junction depth of the pn junction between P+1 region and the N region).
The advantage is to obtain a device that is low cost and high reliability (i.e. see at least paragraph 0011).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the unidirectional transient voltage suppression diode as taught by Jiang et al with the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate as taught by Wang et al in order to obtain a device that is low cost and high reliability.
In addition, Zhang et al discloses an insulating layer (i.e. 5) between barrier layer (i.e. 4) and metal layer (i.e. 7) (see at least Figure 1).
The advantage is to obtain a device that can withstand voltage on the pn junction (i.e. see at least paragraph 0013).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the unidirectional transient voltage suppression diode as taught by Jiang et al with an insulating layer between barrier layer and metal layer as taught by Zhang et al.
In re claim 25, Jiang et al discloses a unidirectional transient voltage suppression diode, comprising: a substrate (i.e. 10) of a first conductivity type (i.e. in this case, p-type), and a first implantation region (i.e. one of the 30) and a second implantation region (i.e. the other 30) of a second conductivity type (i.e. in this case, n-type); wherein the first implantation region is disposed on a front side of the substrate, the second implantation region is disposed on a back side of the substrate (i.e. see at least Figure 6), and a barrier layer (i.e. 40) on a front surface of the substrate from the bottom up; first metal (i.e. 50) is led out of the first implantation region as a first electrode, and second metal (i.e. 60) is led out of the second implantation region on the back side and the substrate respectively as a second electrode, so that the second implantation region on the back side of the substrate is short-circuited with the substrate (i.e. see at least Figure 6); and the first conductivity type is different from the second conductivity type (i.e. in this case, p-type and n-type are different).
Jiang et al does not explicitly disclose a trough; the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate; an insulation layer with the barrier layer arranged in sequence on a front surface of the substrate from the bottom up; the insulation layer is disposed between the barrier layer and a first metal layer.
However, Wang et al discloses a trench in the substrate 4 (i.e. see at least Figure 1); the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate (i.e. see at least Figure 1 showing P+1 region is located on the front surface of the substrate 4, the P+2 region is located on the back surface of the substrate, and the junction depth of the pn junction between the P+2 region and an N region is less than the junction depth of the pn junction between P+1 region and the N region).
The advantage is to obtain a device that is low cost and high reliability (i.e. see at least paragraph 0011).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the unidirectional transient voltage suppression diode as taught by Jiang et al with a trench and the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate as taught by Wang et al in order to obtain a device that is low cost and high reliability.
In addition, Zhang et al discloses an insulating layer (i.e. 5) between barrier layer (i.e. 4) and metal layer (i.e. 7) (see at least Figure 1).
The advantage is to obtain a device that can withstand voltage on the pn junction (i.e. see at least paragraph 0013).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the unidirectional transient voltage suppression diode as taught by Jiang et al with an insulating layer between barrier layer and metal layer as taught by Zhang et al.
In re claim 30, Jiang et al discloses a manufacturing process comprising: forming a barrier layer (i.e. 40) on a substrate (i.e. 10) of a first conductivity type (i.e. in this case, p-type); sequentially forming a first implantation region (i.e. topmost 30) on a front side of the substrate and a second implantation region (i.e. bottommost 30) on a back side, wherein the first implantation region and the second implantation region are of the first conductivity type (i.e. in this case, n-type), and the first conductivity type is different from a second conductivity type (i.e. in this case, p-type is different from n-type); and leading first metal (i.e. 50) out of the first implantation region as a first electrode, and leading second metal (i.e. 60) out of the second implantation region and the substrate respectively as a second electrode, so that the second implantation region on the back side of the substrate is short- circuited with the substrate (i.e. see at least Figure 6).
Jiang et al does not explicitly disclose a depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate; forming an insulation layer on top of the barrier layer on the front side of the substrate, wherein the insulation layer is disposed between the barrier layer and a first metal layer.
However, Wang et al discloses the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate (i.e. see at least Figure 1 showing P+1 region is located on the front surface of the substrate 4, the P+2 region is located on the back surface of the substrate, and the junction depth of the pn junction between the P+2 region and an N region is less than the junction depth of the pn junction between P+1 region and the N region).
The advantage is to obtain a device that is low cost and high reliability (i.e. see at least paragraph 0011).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the unidirectional transient voltage suppression diode as taught by Jiang et al with the depth of a pn junction formed between the second implantation region and the substrate is less than depth of a pn junction formed between the first implantation region and the substrate as taught by Wang et al in order to obtain a device that is low cost and high reliability.
In addition, Zhang et al discloses an insulating layer (i.e. 5) between barrier layer (i.e. 4) and metal layer (i.e. 7) (see at least Figure 1).
The advantage is to obtain a device that can withstand voltage on the pn junction (i.e. see at least paragraph 0013).
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified the unidirectional transient voltage suppression diode as taught by Jiang et al with an insulating layer between barrier layer and metal layer as taught by Zhang et al.
Allowable Subject Matter
Claims 20-24, 26-29, and 31-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
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/ANTHONY HO/Primary Examiner, Art Unit 2817