Prosecution Insights
Last updated: April 19, 2026
Application No. 18/570,706

PLATING DEFECTS ESTIMATING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Non-Final OA §101
Filed
Dec 15, 2023
Examiner
JEFFERSON, QUOVAUNDA
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Power Semiconductor Device, Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
88%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
695 granted / 881 resolved
+10.9% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
45 currently pending
Career history
926
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
58.1%
+18.1% vs TC avg
§102
26.7%
-13.3% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 881 resolved cases

Office Action

§101
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because these claims are directed towards an abstract grouping of mental processes, which is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. A discussion of concepts performed in the human mind, as well as concepts that cannot practically be performed in the human mind and thus are not "mental processes", is provided below with respect to point A. As recited in MPEP 2106,04(a)(2) (III), The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011). As the Federal Circuit explained, "methods which can be performed mentally, or which are the equivalent of human mental work, are unpatentable abstract ideas the ‘basic tools of scientific and technological work’ that are open to all.’" 654 F.3d at 1371, 99 USPQ2d at 1694 (citing Gottschalk v. Benson, 409 U.S. 63, 175 USPQ 673 (1972)). See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 71, 101 USPQ2d 1961, 1965 (2012) ("‘[M]ental processes[] and abstract intellectual concepts are not patentable, as they are the basic tools of scientific and technological work’" (quoting Benson, 409 U.S. at 67, 175 USPQ at 675)); Parker v. Flook, 437 U.S. 584, 589, 198 USPQ 193, 197 (1978) Accordingly, in this instance, claims 1-8 contains mental process when they contain limitations that can practically be performed in the human mind, including for example, observations, evaluations, judgments, and opinions. Claim 1 recite limitations pertaining to an observation process (by a measuring step of measuring the physical properties of a surface of the underlying layer) and an evaluation process (by estimating step of estimating a degree of the development of spikes on the underlayer) performed after the observation processes. The limitations of claims 2-8 also contains limitations that pertain to this mental process and are therefore rejected as well. Allowable Subject Matter Claims 9-13 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 9, the prior art fails to anticipate or render obvious the claimed invention including “...teach a measuring step of measuring physical properties of a surface of the underlayer before the plating pre-treatment step and an estimating step of estimating a degree of development of spikes on the underlayer, the spikes resulting from plating, based on the measured physical properties...” in combination with the remaining limitations. Claims 10-13 are dependent upon claim 9 and are therefore allowable. With regards to claim 9, Fujita (et al, US Patent 10,998,436) teaches a semiconductor device manufacturing method, comprising an underlayer forming step of forming an underlayer on a surface of a semiconductor wafer (aluminum layer, column 1, line 50); a plating pre-treatment step of carrying out a plating pre-treatment on the underlayer (column 1, lines 51-52); a plating step of plating the underlayer subjected to the pre-treatment (column 1, lines 49 and 52-53); and discloses the formation of spikes (as aluminum pitting corrosion, column 1, lines 54-56). Fujita fails to teach a measuring step of measuring physical properties of a surface of the underlayer before the plating pre-treatment step; and an estimating step of estimating a degree of development of spikes on the underlayer, the spikes resulting from plating, based on the measured physical properties. While Lin (et al, US Patent Application Publication 2024/0242946) teaches a measuring step of measuring physical properties of a surface of the underlayer before the plating pre-treatment step (figure 1, step 13), there is no teaching, suggestion, or motivation in which to combine these teachings to arrive at the claimed limitation since Lim performs this process to measure sheet resistance for subsequent low plasma treating on additional structures within the semiconductor device. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 9-13 have been found to be allowable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. QVJ /DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Dec 15, 2023
Application Filed
Mar 17, 2026
Non-Final Rejection — §101 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
88%
With Interview (+8.7%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 881 resolved cases by this examiner. Grant probability derived from career allow rate.

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