Prosecution Insights
Last updated: October 04, 2026
Application No. 18/570,706

PLATING DEFECTS ESTIMATING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Non-Final OA §102§103
Filed
Dec 15, 2023
Priority
Sep 29, 2021 — JP 2021-159508 +1 more
Examiner
JEFFERSON, QUOVAUNDA
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Power Semiconductor Device, Ltd.
OA Round
2 (Non-Final)
79%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
722 granted / 910 resolved
+11.3% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
33 currently pending
Career history
938
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
60.3%
+20.3% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
9.3%
-30.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 910 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abe et al, CN111052330A (as cited by Applicant). Regarding claim 1, Abe teaches a measuring step of measuring physical properties of a surface of an underlayer before a plating pre-treatment step of carrying out a plating pre-treatment on the underlayer (called a pre-surface defect measuring step); and a determining step of determining that occurrence of spikes (which are defects) on the underlayer is small based on the measured physical properties before the formation of a plating film (defects determining process, which evaluates defects induced by processing, such as polishing, as stated in the abstract). Regarding claim 2, Abe the measuring step is a step of making optical measurement on a surface of the underlayer (this limitation is met by looking for defects using Surfscan SP5 manufactured by KLA-Tencor Corporation). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe as applied to claim 1 above, and further in view of Bae, KR 10-0729034 Regarding claims 3 and 4, Abe fails to teach when reflectance on a surface of the underlayer is equal to or larger than a threshold, the degree of development of spikes is determined to be low and wherein when brightness of a surface of the underlayer is equal to or larger than a threshold, the degree of development of spikes is determined to be low. However, Bae teaches that the amount of reflected light incident on the detector decreases below a predetermined amount or the brightness of the surface of the substrate is low, it can be determined /detected as a macroscopic defect in the substrate (see under “Tech Problem”) which would infer that a reflectance on a surface brightness of a surface is equal to or larger than a threshold would mean that the amount of defects would be low or near zero) so that the wafer inspection time is short and quick inspection and since there is no need for a separate processor, the manufacturing cost can be reduced. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bae with that of Abe because the process of Bae allows for quicker and shorter inspection times for substrates, which decreases manufacturing costs. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe as applied to claim 1 above, and further in view of Jie et al, WO 2009/099776 Regarding claim 5, Abe fails to teach the measuring step is a step of making X-ray diffraction measurement on a surface of the underlayer. However, Jie teaches that x-ray photoelectron spectroscopy (XPS) is an alternative, yet generally-known apparatus that is commonly-used in the art for measure properties of the surface of substrates, such as film defects or contaminations [0065]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jie with that of Abe because x-ray photoelectron spectroscopy (XPS) is an alternative, yet generally-known apparatus that is commonly-used in the art for measure properties of the surface of substrates, such as film defects or contaminations Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe as applied to claim 1 above, and further in view of Takase et al, US Patent 6,028,011 Regarding claim 8, Abe fails to teach the plating is nickel plating or nickel alloy plating. Takase teaches the plating is nickel plating or nickel alloy plating (claim 1, step d) because nickel is one of several conventional materials that are used within a semiconductor device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Takase with that of Abe because nickel is one of several conventional materials that are used within a semiconductor device. Allowable Subject Matter Claim 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. With regards to claim 6, the cited prior art(s) of record teach all of the limitations presented, but fail to recite the limitation above. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. With regards to claim 7, while the reference of Takase teaches forming an aluminum layer on a silicon substrate, the combination of Takase with that of Abe still fails to teach the steps of determining step of determining that occurrence of spikes on the aluminum underlayer is small based on the measured physical properties. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Claims 9-13 are allowed. Regarding claim 9, the prior art fails to anticipate or render obvious the claimed invention including “...teach a measuring step of measuring physical properties of a surface of the underlayer before the plating pre-treatment step and an estimating step of estimating a degree of development of spikes on the underlayer, the spikes resulting from plating, based on the measured physical properties...” in combination with the remaining limitations. Claims 10-13 are dependent upon claim 9 and are therefore allowable. With regards to claim 9, Fujita (et al, US Patent 10,998,436) teaches a semiconductor device manufacturing method, comprising an underlayer forming step of forming an underlayer on a surface of a semiconductor wafer (aluminum layer, column 1, line 50); a plating pre-treatment step of carrying out a plating pre-treatment on the underlayer (column 1, lines 51-52); a plating step of plating the underlayer subjected to the pre-treatment (column 1, lines 49 and 52-53); and discloses the formation of spikes (as aluminum pitting corrosion, column 1, lines 54-56). Fujita fails to teach a measuring step of measuring physical properties of a surface of the underlayer before the plating pre-treatment step; and an estimating step of estimating a degree of development of spikes on the underlayer, the spikes resulting from plating, based on the measured physical properties. While Lin (et al, US Patent Application Publication 2024/0242946) teaches a measuring step of measuring physical properties of a surface of the underlayer before the plating pre-treatment step (figure 1, step 13), there is no teaching, suggestion, or motivation in which to combine these teachings to arrive at the claimed limitation since Lim performs this process to measure sheet resistance for subsequent low plasma treating on additional structures within the semiconductor device. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 9-13 have been found to be allowable. Response to Arguments Applicant’s arguments with respect to claim(s) 1 concerning the 35 USC 103 have been considered but are moot because claim 1 has been amended and overcomes the previous rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. QVJ /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Dec 15, 2023
Application Filed
Mar 20, 2026
Non-Final Rejection mailed — §102, §103
Jun 22, 2026
Response Filed
Sep 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
79%
Grant Probability
88%
With Interview (+8.7%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 910 resolved cases by this examiner. Grant probability derived from career allowance rate.

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