Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15, 17-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goldie et al. [US 2021/0334445 A1].
Claims 1-15, 17-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Goldie et al. [US 2021/0334445 A1].
The applied reference has a common Applicant and Inventor(s) with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Taking claim 1 as exemplary of claims 1 and 17-18 [0018, 0091, 0139-0155], a method performed by one or more computers, the method comprising:
training a node placement neural network through reinforcement learning [0064], wherein the node placement neural network is configured to, at each of a plurality of time steps [0036, 0056], receive an input representation comprising data representing a current state of a placement of a netlist of nodes on a surface of an integrated circuit chip as of the time step [0066] and process the input representation to generate a score distribution over a plurality of positions on the surface of the integrated circuit chip [0057, 0094, 0098, 0099], and wherein the training comprises, at each of a plurality of training steps:
obtaining a batch comprising respective netlist data for each of one or more training netlists [0062 batch normalization layers can optionally be included in the policy neural network], wherein each training netlist corresponds to a respective training integrated circuit chip and specifies a connectivity on the corresponding training integrated circuit chip between a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the corresponding integrated circuit chip [0038, 0066], and wherein the plurality of nodes comprise macro nodes representing macro components and standard cell nodes representing standard cell components [0098, 0099, 0113-0115];
identifying, for each training netlist, a subset of the macro nodes specified in the training netlist to be placed using the node placement neural network [0063 a current state, i.e. starting from the current, partial placement];
for each of the training netlists [0063 of a current state]:
generating a partial placement by placing macro nodes from the identified subset for the training netlist according to a macro node order for the training netlist using the node placement neural network until a termination criterion is satisfied [0032-0037, 0131 the system can order the macro nodes, 0113-0116 placement at various stages, until a termination criterion is satisfied is inherent to 0118 optimize an objective function and 0118 maximize the reward];
generating a placement by placing, using a default placer, the standard cell nodes in the training netlist and any remaining macro nodes in the training netlist that have not been placed in the partial placement for the training netlist [0045-0047, 0122, 0123-0126, FIGS. 2 and 3];
generating a reward function value of a reward function that measures a quality of the placement [0063, 0087-0088, 0099, 0122]; and
training the node placement neural network through reinforcement learning using the reward function values for the training netlists [0119-0122].
As per claims 2 and 19, wherein generating a partial placement by placing macro nodes from the identified subset for the training netlist according to a macro node order for the training netlist using the node placement neural network until a termination criterion is satisfied comprises, at each particular time step of a plurality of time steps: generating, from the netlist data for the training netlist, an input representation that characterizes a current state of a placement of the training netlist as of the particular time step; processing the input representation using the node placement neural network to generate a score distribution over a plurality of positions on the surface of the integrated circuit chip; assigning a macro node to be placed at the particular time step to a particular position from the plurality of positions using the score distribution; and determining whether the termination criterion is satisfied after the macro node is assigned to the particular position [following from the above citations, FIG. 2 iterations 0070-0077].
As per claims 3 and 20, wherein the termination criterion is satisfied when each macro node from the identified subset has been placed using the node placement neural network [0044, 0094, 0099 result in a chip that is manufactured].
As per claims 4 and 21, wherein generating a partial placement by placing macro nodes from the identified subset for the training netlist in respective locations according to a macro node order for the training netlist using the node placement neural network until a termination criterion is satisfied comprises: after placing each macro node, determining whether the partial placement will enter an infeasible state [0050 the legalization engine is interpreted to provide for high quality placements, 0087-0088, 0098-0099 training with a reward function that measures quality is interpreted to result in a chip that is manufactured], wherein an infeasible state occurs when two macro nodes overlap on the surface of the training integrated circuit chip [0047 the graph placement technique can be any appropriate technique for placing nodes of a graph, optionally, the engine also introduces a repulsive force between overlapping nodes to reduce placement density]; and in response to determining that the partial placement will enter an infeasible state, determining that the termination criterion is satisfied [an infeasible state is interpreted as the chip not being manufactured].
As per claim 5, wherein, after placing each macro node, determining whether the partial placement will enter an infeasible state comprises: determining that the partial placement will enter the infeasible state when a next macro node in the macro node order cannot be placed without overlapping with another, already-placed macro node in the partial placement [0047 the graph placement technique can be any appropriate technique for placing nodes of a graph, optionally, the engine also introduces a repulsive force between overlapping nodes to reduce placement density, 0050 the legalization engine is interpreted to provide for high quality placements, 0087-0088, 0098-0099 training with a reward function that measures quality is interpreted to result in a chip that is manufactured, an infeasible state is interpreted as the chip not being manufactured].
As per claim 6, wherein the default placer is an analytical placer [0108 since the reward function includes a timing term it is interpreted that the nodes are analytically placed].
As per claim 7, wherein the reward function includes a term that measures a degree of overlap of the macro nodes in the placement [0047 the graph placement technique can be any appropriate technique for placing nodes of a graph, optionally, the engine also introduces a repulsive force between overlapping nodes to reduce placement density].
As per claim 8, wherein, for each training step and for each training netlist, the identified subset includes all of the macro nodes in the training netlist [0019 netlist data may be different depending on the desired function of the chip, 0020 netlist data, each node corresponds to a respective proper subset, 0021 a final computer chip placement places all of the nodes in the netlist data, 0066 all of the nodes in the netlist].
As per claim 9, wherein identifying, for each training netlist, a subset of the macro nodes specified in the training netlist to be placed using the node placement neural network comprises:
determining a portion of the macro nodes in the training netlist to be included in the subset [0063 a current state, starting from the current partial placement] according to a schedule [0131 the system can order the macro nodes] that maps data characterizing the training step to the portion of the macro nodes for each training netlist in the batch for the training step that should be included in the subset [0062 the policy network can have any appropriate architecture, including batch normalization layers, to map the encoded representation to a score distribution as per FIG. 2].
As per claim 10, wherein the schedule maps the first training step to a pre-determined portion that is less than all of the macro nodes in the training netlist and maps a later training step to a portion that corresponds to all of the macro nodes in the training netlist [following from above FIG. 2 performs the functional limitations].
As per claim 11, wherein, when placing both macro nodes and standard cells from a given netlist [0022, 0066, 0078, 0122], the default placer generates placements that include overlap between two or more of the macro nodes [0047 the graph placement technique can be any appropriate technique for placing nodes of a graph, optionally, the engine also introduces a repulsive force between overlapping nodes to reduce placement density, thus by using force-directed placement overlap is included].
As per claim 12, further comprising:
after training the node placement neural network through reinforcement learning [0119]:
receiving new netlist data [0123];
fine-tuning the trained node placement neural network on the new netlist data through reinforcement learning [0126]; and
generating an integrated circuit placement for the new netlist data using the fine-tuned node placement neural network, comprising placing a respective node from the new netlist data at each of a plurality of time steps using score distributions generated by the fine-tuned node placement neural network [0126].
As per claim 13, further comprising:
after training the node placement neural network through reinforcement learning [0119]:
receiving new netlist data [0123]; and
generating an integrated circuit placement for the new netlist data using node placement neural network, comprising placing a respective node from the new netlist data at each of a plurality of time steps using score distributions generated by the node placement neural network [0124].
As per claim 14, wherein:
the node placement neural network includes:
an encoder neural network that is configured to receive the input representation and process the input representation to generate an encoded representation [FIG. 2 element 210, 0011, 0060, 0094, FIG. 3], and
a policy neural network that is configured to process the encoded representation to generate the score distribution [FIG. 2 element 220, 0011, 0061, 0094, FIG. 3].
As per claim 15, further comprising:
prior to training the node placement neural network through reinforcement learning, pre- training the encoder neural network through supervised learning [0090, 0097, 0115, 0125, FIG. 3].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The Examiner notes that the Written Opinion of the International Searching Authority finds that none of the prior art anticipates the features of the dependent claims 9 and 10. However, given a broadest reasonable interpretation of the broadly claimed subject matter, the Examiner presented the above citations and reasonings to further differentiate the subject matter disclosed as the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851
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