DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Withdrawn Rejections
Applicant’s arguments, see remarks filed 02/19/2026, with respect to the rejection(s) of claim(s) 1-2 under 35 USC 102 over Ebara et al (US 2009/0007839) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ebara et al (US 2009/0000535).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 depends from independent claim 1. Claim 1 requires “produce the nitrogen-doped single crystal ingot with only the pure vacancy area.” However, claim 6 claims three different pulling speeds that produces an ingot that is not a ingot with only the pure vacancy area. Claim 6 recites “based on the distribution position I of the pure vacancy area in the reference nitrogen- doped single crystal silicon ingot, performing a pulling using a reference pulling speed Vo;based on the distribution position II of the pure interstitial area surrounding the pure vacancy area in the reference nitrogen-doped single crystal silicon ingot, performing a pulling using a first target pulling speed V1;based on the distribution position III of the pure vacancy area surrounding the pure interstitial area in the reference nitrogen-doped single crystal silicon ingot, performing a pulling using a second target pulling speed V2; and based on the distribution position IV of the pure interstitial area in the reference nitrogen- doped single crystal silicon ingot, performing a pulling using a third pulling speed V3.” It is unclear how to satisfy all of the limitations of claim 6 when claim 1 explicitly require an ingot with only the pure vacancy area. Claim 7 depends from claim 6; therefore, the same argument applies. For the purposes of expediating examination, the claims are interpreted as not allowing other growth defects because claim was explicitly amended to require “only the pure vacancy area.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ebara et al (US 2009/0000535).
Ebara et al teaches a method for producing a nitrogen-doped single crystal silicon ingot, comprising: after cutting a reference nitrogen-doped single crystal silicon ingot into sample silicon wafers (abstract; [0002], [0013], [0037]-[0042], [0073], [0093] and claims 3 and 6, teaches a single crystal silicon wafer having a nitrogen concentration and a wafer is sliced from a silicon single crystal ingot grown by the CZ method), selecting a plurality of silicon wafers to be tested and evaluating a distribution of defect areas in the plurality of silicon wafers to be tested (abstract; [0005]-[0021], [0037]-[0048], Figs 1, 2a, 2b and 2c teaches evaluation of crystal defects showing defect distribution of wafers sliced from an ingot); wherein the defect areas comprise any of the group consisting of a pure vacancy area, a pure interstitial area, and an alternating distribution area of a pure vacancy area and a pure interstitial area (see abstract; [0005]-[0021], [0037]-[0048], Figs 1, 2a, 2b and 2c teaches an Nv region over an entire plane of the wafer where Va (vacancies) are dominant (Fig 2a); Fig 2c teaches Ni region where I (interstitial) are dominant); and Fig 2b teaches an Nv region in a central portion and an Ni in an outer circumferential portion); determining a distribution position of each defect area in the reference nitrogen-doped single crystal silicon ingot based on the distribution of the defect areas in the plurality of silicon wafers to be tested (Fig 1 and 2a, 2b and 2c shows the defect distribution of wafers sliced along the axis of the ingot); in a production process of the nitrogen-doped single crystal silicon ingot, performing a pulling at a set target pulling speed corresponding to each defect area which refers to the distribution position of each defect area in the reference nitrogen-doped single crystal silicon ingot, to produce the nitrogen-doped single crystal silicon ingot (abstract; Fig 1; [0005]-[0021], [0037]-[0048], Figs 1, 2a, 2b and 2c teaches the pulling rate has a direction relationship with defect and the single crystal is pulled up while controlling the growth rate where an Nv region can be formed over an entire plane of a wafer by determining pulling rate in advance by slicing an ingot in which the pulling rate is changed and sliced wafers are evaluated for defects). Ebara et al teaches the silicon single crystal ingot can be pulled up in such a manner that the whole area in the radial direction becomes Nv region, and an explicit example of controlling the pulling rate to become 0.595 mm/min (the position of A-A in FIG. 1) and slice the silicon single crystal ingots in a radial direction to prepare Nv wafers ([0039]-[0040], [0110]), which reads on a performing a pulling at a set target pulling speed corresponding to each defect area which refers to the distribution position of each defect area in the reference nitrogen-doped single crystal silicon ingot, to produce the nitrogen-doped single crystal silicon ingot with only the pure vacancy area.
Referring to claim 2, Ebara et al teaches selecting the plurality of silicon wafers to be tested and evaluating the distribution of the defect areas in the plurality of silicon wafers to be tested after cutting the reference nitrogen-doped single crystal silicon ingot into the sample silicon wafers comprises: producing the reference nitrogen-doped single crystal silicon ingot with a reference pulling speed, and cutting the reference nitrogen-doped single crystal silicon ingot to obtain the sample silicon wafers; selecting silicon wafers from the plurality of sample silicon wafers located at different positions of the reference nitrogen-doped single crystal silicon ingot as the silicon wafers to be tested, and evaluating the distribution of the defect areas in the plurality of silicon wafers to be tested (Fig 1 and 2a, 2b, 2c teaches the ingot is pulled at a pulling speed and wafers a sliced at different locations to produce wafers which are evaluated for defects and shown in Fig 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ebara et al (US 2009/0000535), as applied to claims 1-2 above, and further in view of Jin et al (CN 111624460), an English computer translation (CT) is provided.
Ebara et al teaches all of the limitations of claim 3, as discussed above, except evaluating the distribution of the defect areas in the plurality of silicon wafers to be tested comprises: obtaining minority carrier lifetime data on surfaces of the plurality of silicon wafers to be tested, and generating minority carrier lifetime maps based on the minority carrier lifetime data on the surfaces of the plurality of silicon wafers to be tested; evaluating the distribution of the defect areas in the plurality of silicon wafers to be tested based on the minority carrier lifetime maps.
In a method of detecting defect distribution regions in single-crystal silicon, Jin et al teaches a minority carrier lifetime test is performed on a plurality of silicon wafers (CT [0011]-[0015], [0026]-[0027]). Jin et al teaches the distribution areas of various defects can be determined, specifically including V-rich, P-band, Pv, Pi, and I-rich regions from the measure minority carrier lifetime values (CT [0053]-[0056]), which clearly suggests obtaining minority carrier lifetime data on surfaces of the plurality of silicon wafers to be tested, and generating minority carrier lifetime maps based on the minority carrier lifetime data on the surfaces of the plurality of silicon wafers to be tested; evaluating the distribution of the defect areas in the plurality of silicon wafers to be tested based on the minority carrier lifetime maps. Jin et al teaches the minority carrier detection method simplifies the detection process, improves detection efficiency, and reduces detection costs (CT [0056]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Ebara et al by obtaining minority carrier lifetime data on surfaces of the plurality of silicon wafers to be tested, and generating minority carrier lifetime maps based on the minority carrier lifetime data on the surfaces of the plurality of silicon wafers to be tested; evaluating the distribution of the defect areas in the plurality of silicon wafers to be tested based on the minority carrier lifetime maps, as taught by Jin et al, because the minority carrier detection method simplifies the detection process, improves detection efficiency, and reduces detection costs, while determining V-rich, P-band, Pv, Pi, and I-rich regions from the measure minority carrier lifetime values.
Referring to claim 4, The combination of Ebara et al and Jin et al does not explicitly teach evaluating the distribution of the defect areas in the plurality of silicon wafers to be tested based on the minority carrier lifetime maps comprises: when the minority carrier lifetime map is a map in a circle shape and with a long lifetime, determining the silicon wafer to be tested corresponding to the map in the circle shape with the long lifetime to be a first silicon wafer to be tested containing only the pure vacancy area; and when the minority carrier lifetime map is a map in a ring shape and with the short lifetime, determining the silicon wafer to be tested corresponding to the map in the ring shape and with the short lifetime to be a second silicon wafer to be tested containing the pure interstitial area surrounding the pure vacancy area; and when the minority carrier lifetime map is map in a ring shape and with a long lifetime, determining the silicon wafer to be tested corresponding to the map in the ring shape and with the long lifetime to be a third silicon wafer to be tested containing the pure vacancy area surrounding the pure interstitial area; and when the minority carrier lifetime map is a map in a circle shape and with a short lifetime, determining the silicon wafer to be tested corresponding to the map in the circle shape and with the short lifetime to be a fourth silicon wafer to be tested containing only the pure interstitial area. The combination of Ebara et al and Jin et al teaches the distribution areas of various defects can be determined, specifically including V-rich, P-band, Pv, Pi, and I-rich regions from the measure minority carrier lifetime values (Jin CT [0053]-[0056]), therefore, the relationship between short lifetime and long lifetime and vacancies and interstitial regions would be expected using a similar method of using minority carrier lifetime values to determine defect regions, and Ebara et al teaches Pv, Pi and mixed Pi/Pv region having a circle shape and ring shapes (Ebara Fig 2a, 2b and 2c).
Referring to claim 5, the combination of Ebara et al and Jin et al teaches determine defect distribution of a plurality of wafers sliced from an ingot, wherein the wafers Pv, Pi, or mixed Pv/Pi (Ebara Fig 1, and 2a, 2b and 2c).
Referring to claim 6, the combination of Ebara et al and Jin et al teaches determine defect distribution of a plurality of wafers sliced from an ingot, wherein the wafers Pv, Pi, or mixed Pv/Pi is dependent on the pulling speed (Ebara Fig 1, and 2a, 2b and 2c); and pulling the ingot a desired speed to produce a wafer with a desired defect distribution.
Referring to claim 7, the combination of Ebara et al and Jin et al does not explicitly teach the first target pulling speed V1 is the reference pulling speed Vo +0.001mm/min to 0.002mm/min; and the second target pulling speed V2 is the reference pulling speed Vo + 0.002mm/min to 0.003mm/min; and the third target pulling speed V3 is the reference pulling speed Vo + 0.003mm/min to 0.006mm/min. The combination of Ebara et al and Jin et al teaches the pulling speed is a result effective variable in controlling the defect distribution; therefore, It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Ebara et al and Jin et al by optimizing the pulling speed to obtain the claimed target pulling speed by conducting routine experimentation of a result effective variable to obtain a wafer having a desired defect distribution.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW J SONG whose telephone number is (571)272-1468. The examiner can normally be reached Monday-Friday 10AM-6PM.
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/ Primary Examiner, Art Unit 1714
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