DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ebihara et al. (US 20210005744 A1, hereinafter Ebihara), and further in view of Fujiwara et al. (US 20180090612 A1, hereinafter Fujiwara).
Regarding independent claim 1, Ebihara discloses in Ebihara FIG. 1 and 5A-5J and associated text a silicon carbide MOSFET device (Ebihara [0002]), comprising: an epitaxial wafer, which comprises a semiconductor substrate and epitaxial layers disposed on a surface of the semiconductor substrate (substrate 1, and epitaxially grown layers 2-8 (Ebihara [0092]-[0105], FIG. 5A-5G) are considered the epitaxial wafer); and a well region (layers 3, 5, and 6), a source region (source region 7), and a trench gate (gate trench 9), which are in the epitaxial layers (as shown), wherein: the trench gate comprises a gate disposed in a trench at a surface of the epitaxial layers facing away from the semiconductor substrate (gate trench 9 has the aforementioned structure), and a gate dielectric layer is disposed between the gate electrode and the trench (gate insulation film 10, gate electrode 11, and gate trench 9 have the aforementioned structure); the source region surrounds the trench and is in contact with sidewalls of the trench (source region 7 has the aforementioned structure); the well region comprises a first layer, a second layer, and a third layer, which are arranged in the above-listed sequence along a direction pointing from the semiconductor substrate to the source region (layers 3, 5, and 6, corresponding to the first, second, and third layer respectively, have the aforementioned structure); a bottom of the trench is disposed higher than the first layer and lower than the third layer (gate trench 9 and layers 3 and 6 have the aforementioned structure); the third layer surrounds the trench and is in contact with the sidewalls of the trench (layer 6 has the aforementioned structure); one or more doped regions are disposed in the epitaxial layers and beneath the trench (JFET portion 2a is n-doped (Ebihara [0061]) and located as claimed), and the first layer surrounds each of the one or more doped region and is in contact with said doped region (deep layer 3 has the aforementioned structure with respect to JFET portion 2a); a part of the epitaxial layers is disposed between the first layer and the third layer (current dispersion layer 4 is located between layers 3 and 6), and the second layer is disposed on two sides of the part of the epitaxial layers (connection layer 5 is on either side of current dispersion layer 4), and the first layer, the second layer, and the third layer have the same polarity (layers 3, 5, and 6 are all of the p-type). Ebihara does not explicitly disclose a shielding layer is disposed in the part of the epitaxial layers and is configured to protect a bottom of the trench gate; and the shielding layer is disposed beneath the trench, and dopants in the shielding layer has a same polarity as dopants in each of the first layer, the second layer, and the third layer.
However, in the same field of endeavor, Uchida discloses in Uchida FIG. 27-28 and associated text a shielding layer is disposed in the part of the epitaxial layers and is configured to protect a bottom of the trench gate (third impurity region 70 is in second drift region portion 22, corresponding to the part of the epitaxial layers, and relieves electric field concentration at the gate trench 6 (Uchida [0127])); and the shielding layer is disposed beneath the trench (third impurity region 70 is below gate trench 6), and dopants in the shielding layer has a same polarity as dopants in each of the first layer and the third layer (third impurity region 70, first impurity region 50, and body region 13 are of the second conductivity type (Uchida [0047] and [0037])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the MOSFET structure of Ebihara with the shielding layer of Uchida such that the shielding layer has the same polarity as the first, second, and third layers of the well region to provide a silicon carbide MOSFET wherein the gate trench is shielded from high concentration electric fields (Uchida [0127]).
Regarding dependent claim 2, Ebihara, as modified by Uchida, further discloses in Ebihara FIG. 1 and associated text a vertical projection of the one or more doped regions on the semiconductor substrate is located within a vertical projection of the trench on the semiconductor substrate, and the vertical projection of the trench on the semiconductor substrate is located within a vertical projection of the part of the epitaxial layers on the semiconductor substrate; and there is a non-zero distance between a boundary of the vertical projection of the trench and a boundary of the vertical projection of the part of the epitaxial layers (the aforementioned structure is shown in Ebihara FIG. 1 and further illustrated in the following annotated figure).
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Regarding dependent claim 5, Ebihara, as modified by Uchida, further discloses in Ebihara FIG. 10 and associated text the one or more doped regions are a plurality of doped regions arranged sequentially along a first direction, which is parallel with the semiconductor substrate and parallel with an extending direction of the trench (a plurality of JFET portion 2a, corresponding to the one or more doped regions, is arranged along the extending direction of the gate trench 9).
Regarding dependent claim 6, Ebihara, as modified by Uchida, further discloses in Uchida FIG. 27-28 and associated text along a direction perpendicular to the semiconductor substrate, a distance from the shielding layer to the bottom of the trench is smaller than a distance from the shielding layer to the first layer (the relative distances between the shielding layer 70, the bottom portion of the trench 42, and the first layer 50 are as described in Uchida FIG. 27-28).
Regarding dependent claim 7, Ebihara, as modified by Uchida, further discloses in Uchida FIG. 27-28 and associated text the shielding layer is in contact with the bottom of the trench (the shielding layer 70 is in contact with the bottom portion of the trench 42 as described in Uchida FIG. 27-28).
Regarding dependent claim 8, Ebihara, as modified by Uchida, further discloses in Ebihara FIG. 1 and associated text the second layer comprises a first part and a second part, which are disposed on two sides, respectively, of the trench; and the first part and the second part each is an integral structure (layer 5 is on both sides of gate trench 9 and each part is a structure that is integral according to the definition of integral: “included as part of a whole rather than supplied separately”, where each part is included as a part of the whole structure of the semiconductor device).
Regarding dependent claim 12, Ebihara, as modified by Uchida, further discloses in Ebihara FIG. 1 and 5A-5J and Uchida FIG. 27-28 and associated text a method for manufacturing the silicon carbide MOSFET device (Ebihara [0002]) according to claim 1, comprising: providing an epitaxial wafer, which comprises a semiconductor substrate and epitaxial layers disposed on a surface of the semiconductor substrate (Ebihara: substrate 1, and epitaxially grown layers 2-8 (Ebihara [0092]-[0105], FIG. 5A-5G) are considered the epitaxial wafer); forming a well region (Ebihara: layers 3, 5, and 6), a source region (Ebihara: source region 7), and a trench gate (Ebihara: gate trench 9) in the epitaxial layers (as shown), wherein: the trench gate comprises a gate disposed in a trench at a surface of the epitaxial layers facing away from the semiconductor substrate (Ebihara: gate trench 9 has the aforementioned structure), and a gate dielectric layer is disposed between the gate electrode and the trench (Ebihara: gate insulation film 10, gate electrode 11, and gate trench 9 have the aforementioned structure); the source region surrounds the trench and is in contact with sidewalls of the trench (Ebihara: source region 7 has the aforementioned structure); the well region comprises a first layer, a second layer, and a third layer, which are arranged in the above-listed sequence along a direction pointing from the semiconductor substrate to the source region (Ebihara: layers 3, 5, and 6, corresponding to the first, second, and third layer respectively, have the aforementioned structure); a bottom of the trench is higher than the first layer and lower than the third layer (Ebihara: gate trench 9 and layers 3 and 6 have the aforementioned structure); the third layer surrounds the trench and is in contact with the sidewalls of the trench (Ebihara: layer 6 has the aforementioned structure); one or more doped regions are disposed in the epitaxial layers and beneath the trench (Ebihara: JFET portion 2a is n-doped (Ebihara [0061]) and located as claimed), and the first layer surrounds each of the one or more doped region and is in contact with said doped region (Ebihara: deep layer 3 has the aforementioned structure with respect to JFET portion 2a); a part of the epitaxial layers is disposed between the first layer and the third layer (Ebihara: current dispersion layer 4 is located between layers 3 and 6), and the second layer is disposed on two sides of the part of the epitaxial layers (Ebihara: connection layer 5 is on either side of current dispersion layer 4); a shielding layer is disposed in the part of the epitaxial layers and is configured to protect a bottom of the trench gate (Uchida: third impurity region 70 is in second drift region portion 22, corresponding to the part of the epitaxial layers, and relieves electric field concentration at the gate trench 6 (Uchida [0127])); and the shielding layer is disposed beneath the trench (Uchida: third impurity region 70 is below gate trench 6), and dopants in the shielding layer has a same polarity as dopants in each of the first layer, the second layer, and the third layer (the references as combined have the aforementioned limitation).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ebihara, and further in view of Uchida and Yamamoto et al. (US 20090261350 A1, hereinafter Yamamoto).
Regarding dependent claim 9, Ebihara, as modified by Uchida, discloses in Ebihara FIG. 1 and associated text the second layer comprises a first part and a second part, which are disposed on two sides, respectively, of the trench (layer 5 is on both sides of gate trench 9). They do not explicitly disclose the first part of the second layer and the second part each comprises a plurality of sub-regions arranged sequentially along a first direction, which is parallel with the semiconductor substrate and parallel with an extending direction of the trench; and a current expanding region is disposed between each pair of sub-regions which are adjacent along the first direction among the plurality sub-regions, and dopants in the current expanding region has an opposite polarity to dopants in the a plurality of sub-regions.
However, in the same field of endeavor, Yamamoto discloses in Yamamoto FIG. 1 and 2A-2D and associated text the first part of the second layer and the second part each comprises a plurality of sub-regions arranged sequentially along a first direction, which is parallel with the semiconductor substrate and parallel with an extending direction of the trench (side portions of deep layer 10 are sub-regions corresponding to the second layer are arranged sequentially in the direction described as shown in Yamamoto FIG. 1 and the annotated figure below); and a current expanding region is disposed between each pair of sub-regions which are adjacent along the first direction among the plurality sub-regions, and dopants in the current expanding region has an opposite polarity to dopants in the a plurality of sub-regions (regions of n-doped drift layer 2 are between sub-regions of p-doped deep layer 10 in the y-direction, which corresponds to the first direction described).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Ebihara, as modified by Uchida, with the second layer sub-regions and current spreading regions of Yamamoto to provide a semiconductor device with a reduced electric field concentration in the gate oxide layer (Yamamoto [0011]).
Allowable Subject Matter
Claims 3, 4, 10, 11, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200403066 A1, pertaining to a SiC MOSFET with a connection region between a shielding region and a first layer of a well region, but which does not disclose forming the connection region through the gate trench or the connection region having greater impurity concentration than the well region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897