DETAILED ACTION
The Amendment filed May 08, 2026 has been entered. Claims 1-26 are pending. Claims 21-26 have been added. Claims 10 and 21 are independent.
Drawings
Figure 1 does not include the cross-coupled inverter as claimed in Claim 10. Clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-16 and 21-26 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jung et al. (US 9,552,872).
Regarding independent claim 10, Jung et al. teach a SRAM-bit cell (see e.g., FIG. 4) comprising a first transistor M1 (PG1), a second transistor M2 (PG2), a third transistor M3 (WR2), a fourth transistor M4 (RD2), a fifth transistor M5 (IN1, PMOS), a sixth transistor M6 (IN1, NMOS), a seventh transistor M7 (IN2, PMOS), and an eighth transistor M8 (IN2, NMOS),
wherein a four transistor cross-coupled inverter component includes a first transistor inverter (IN1) and a second transistor inverter (IN2), the first transistor inverter including the fifth transistor M5 and the sixth transistor M6 (inverter logic comprises PMOS and NMOS) connected at a first node Vx (DS1) and the second transistor inverter including the seventh transistor M7 and the eighth transistor M8 (inverter logic comprises PMOS and NMOS) connected at a second node Vy (DS2);
wherein the first transistor M1 (PG1) is a first access transistor in electrical communication with the gates of the seventh transistor M7 and the eighth transistor M8 which are connected together (see IN2), the first transistor M1 also being in electrical communication with a first bit line BL (WBLB);
wherein the second transistor M2 (PG2) is a first additional transistor in electrical communication with the gates of transistor the fifth transistor M5 and the sixth transistor M6 which are connected together (see IN1), the gates of both the first transistor M1 and the second transistor M2 are in electrical communication with a wordline WL1 (WL1); and
wherein the third transistor M3 (WR2) is a second access transistor M3 in electrical communication with the second transistor M2 (PG2) both of which are in electrical communication with the gate of the fourth transistor M4 (RD2) at a dynamic node Vz (LBL), the fourth transistor M4 (RD2) being in electrical communication with line SL (RWLB) and line BLR (RBL), the gate of the third transistor M3 (WR2) is in electrical communication with wordline WL2 (WWL), the third transistor M3 (WR2) is also in electrical communication with second bit line BLB (WBL).
Jung's memory device 100 in Figure 4 includes a write operation pass gate and a read buffer transistor that are commonly connected to conventional six-transistor SRAM bit cells BC1 to BC4. During a memory operation, the memory cell that is activated includes a write operation pass gate and a read buffer transistor that are commonly connected to one of Jung's SRAM cells BC1 to BC4. In other words, one of cells BC1 and BC4 is coupled with the pass gate and buffer transistor to form the claimed SRAM bit cell.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilized the teaching of Jung et al. to combine conventional six-transistor SRAM cell, write pass gate, and read buffer transistor to form SRAM bit cells because these conventional technology are well established in the art of the memory devices.
Regarding claim 11, Jung et al. teach the limitations of claim 10.
Jung et al. further teach for the Normal mode of operation, both the wordlines WL1 and WL2 are activated, simultaneously (see FIGS. 5-10, read and write operation circuits and their timing diagrams, and accompanying disclosure).
Regarding claim 12, Jung et al. teach the limitations of claim 10.
Jung et al. further teach during Normal mode, the SL line and the BLR line are kept at about 0V to ensure no current flows through the fourth transistor M4, irrespective of a voltage at its gate (see FIGS. 5-10, read and write operation circuits and their timing diagrams, and accompanying disclosure).
Regarding claim 13, Jung et al. teach the limitations of claim 10.
Jung et al. further teach in augmented mode, two bits of data are simultaneously stored (see FIGS. 5-10, read and write operation circuits and their timing diagrams, and accompanying disclosure).
Regarding claim 14, Jung et al. teach the limitations of claim 10.
Jung et al. further teach SRAM-like static data is stored in the cross-coupled inverter as complementary voltages on nodes Vx and Vy, while the third transistor M3 and the fourth transistor M4 store a DRAM-like data on the dynamic node Vz (see FIGS. 5-10, read and write operation circuits and their timing diagrams, and accompanying disclosure).
Regarding claim 15, Jung et al. teach the limitations of claim 10.
Jung et al. do not explicitly disclose a differential sense amplifier for SRAM in electrical communication with the first bit line BL and the second bit line BLB.
However, Jung’s data out to bit line (claimed first bit line BL) and complimentary bit line (claimed second bit line BLB), and a differential sense amplifier in a read operation is a well-known technology for a type of memory (e.g., SRAM) for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in reading with diff-SA circuits because these conventional technology are well established in the art of the memory devices.
Regarding claim 16, Jung et al. teach the limitations of claim 10.
Jung et al. further teach all transistors are CMOS transistors (FIGS. 4-10, i.e., PMOS and NMOS).
Further, dependent claims 11-14 claims functions of the apparatus independent claim 10, and are rejected under USC 103 as being unpatentable over Jung et al., figures 4-10, which is identical to instance applicant’s figure 1 to which all apparatus claims are supported.
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Because Jung’s apparatus is substantially identical to applicant’s claimed device, the claimed functions are presumed inherent. MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); MPEP 2112.01(I) (quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I).
It appears applicant describes their invention as a method of operating a NAND flash memory. Although a method of operating an old device may be patentable, a novel method of operating does not differentiate an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating a Device Does Not Differentiate Apparatus Claim from the Prior Art.”).
Regarding independent claim 21, Jung et al. teach a SRAM-bit cell (see e.g., FIG. 4) comprising a first transistor M1 (PG1), a second transistor M2 (PG2), a third transistor M3 (WR2), a fourth transistor M4 (RD2), a fifth transistor M5 (IN1, PMOS), a sixth transistor M6 (IN1, NMOS), a seventh transistor M7 (IN2, PMOS), and an eighth transistor M8 (IN2, NMOS),
wherein a four transistor cross-coupled inverter component includes a first transistor inverter (IN1) and a second transistor inverter (IN2), the first transistor inverter including the fifth transistor M5 and the sixth transistor M6 (inverter logic comprises PMOS and NMOS) connected at a first node Vx (DS1) and the second transistor inverter including the seventh transistor M7 and the eighth transistor M8 (inverter logic comprises PMOS and NMOS) connected at a second node Vy (DS2);
wherein the first transistor M1 (PG1) is a first access transistor in electrical communication with the gates of the seventh transistor M7 and the eighth transistor M8 which are connected together (see IN2), the first transistor M1 also being in electrical communication with a first bit line BL (WBLB);
wherein the second transistor M2 (PG2) is a first additional transistor in electrical communication with the gates of transistor the fifth transistor M5 and the sixth transistor M6 which are connected together (see IN1), the gates of both the first transistor M1 and the second transistor M2 are in electrical communication with a wordline WL1 (WL1); and
wherein the third transistor M3 (WR2) is a second access transistor M3 in electrical communication with the second transistor M2 (PG2) both of which are in electrical communication with the gate of the fourth transistor M4 (RD2) at a dynamic node Vz (LBL), the fourth transistor M4 (RD2) being in electrical communication with line SL (RWLB) and line BLR (RBL), the gate of the third transistor M3 (WR2) is in electrical communication with wordline WL2 (WWL), the third transistor M3 (WR2) is also in electrical communication with second bit line BLB (WBL);
wherein the first wordline WL1 (FIG. 4: WL1) and the second wordline WL2 (WWL) are separately controllable, the first wordline WL1 controlling the first transistor M1 (PG1) and the second transistor M2 (PG2) within the single SRAM-bit cell, and the second wordline WL2 controlling the third transistor M3 (WR2) within the single SRAM-bit cell (see FIG. 4 and accompanying disclosure); and
wherein the single SRAM-bit cell is configurable in a Normal mode in which both wordlines WL1 and WL2 are simultaneously activated (FIG. 4: when WW1 and WWL activated) such that the SRAM-bit cell operates as a 6T SRAM bit cell, and an Augmented mode in which the third transistor M3 (WR2) and the fourth transistor M4 (RD2) store a DRAM-like data on the dynamic node Vz (LBL node) simultaneously with SRAM-like static data stored as complementary voltages on nodes Vx (DS1) and Vy (DS2) (see FIGS. 4-10, read and write operation circuits and their timing diagrams, and accompanying disclosure).
Further, claim 21 contains functions of the apparatus, and is rejected under USC 103 as being unpatentable over Jung et al., figures 4-10, which is identical to instance applicant’s figure 1 to which all apparatus claims are supported.
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Because Jung’s apparatus is substantially identical to applicant’s claimed device, the claimed functions are presumed inherent. MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); MPEP 2112.01(I) (quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I).
It appears applicant describes their invention as a method of operating a NAND flash memory. Although a method of operating an old device may be patentable, a novel method of operating does not differentiate an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating a Device Does Not Differentiate Apparatus Claim from the Prior Art.”).
Regarding dependent claims 22-26 are rejected for the same reason set forth above as applied to claims 10-16.
Response to Argument
The applicant’s arguments filed 05/08/2026, have been fully considered but are not persuasive.
The applicant argues that the claimed invention and Jung address fundamentally different problems.
In response to the applicant’s argument, the examiner examines the claimed limitation(s). Independent claim 10 claims an SRAM bit cell and does not claim any means for solving a problem.
The applicant argues that clam 10 recites “a SRAM-bit cell comprising 8 transistors”. Jung’s shared peripheral elements serves four separate bit cells, not to nay single bit cell.
In response to the applicant’s argument, as the applicant acknowledges, Jung’s six SRAM transistors and additional components constitute the claimed a 8-transistor SRAM-bit cell. The applicant claims a single SRAM bit-cell.
The applicant argues the internal topology of the claimed bit cell structure is different from that of Jung, explaining the intermediate dynamic node is a defining structure feature of the claimed invention and is what permits dual-mode operation between and Normal and Augmented modes.
In response to the applicant’s argument, the applicant claims the electrical coupling (claimed communication) between the components, but does not claim the dual-mode operation as asserted.
The applicant argues that the dynamic node Vz and gain-cell dram structure have no counterpart in Jung.
In response the applicant’s arguments, the applicant claims “a DRAM-like data” in dependent claim 14. Independent claim 10 is a claim directed to an apparatus, and Jung discloses all the elements constituting the limiting elements of the claim.
The applicant argues that dual wordlines within a single cell vs shared row/column control.
In response the applicant’s arguments, the applicant does not claim that argument. Independent claim 10 is a claim directed to an apparatus, and Jung discloses all the elements constituting the limiting elements of the claim.
The applicant argues that the examiner’s inherency argument of claims 11-14 fails, explaining the paragraph refers to “Tseng” without citing the reference.
In response the applicant’s arguments, the examiner corrected a typo related to Jung.
The applicant argues that claims 15 and 16 depend from claim 10 is patentable over Jung for the reasons set forth above.
In response to the applicant’s argument, refer to the examiner’s responses set forth above.
Regarding newly added claims 21-26, see the art rejections above.
To better understand the examiner’s responses explained above, see the EXMINER’S MARKUP below.
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Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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