Prosecution Insights
Last updated: April 19, 2026
Application No. 18/571,570

OPTOELECTRONIC DEVICE AND METHOD FOR PROCESSING THE SAME

Non-Final OA §102§103
Filed
Dec 18, 2023
Examiner
GREEN, TELLY D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
AMS-OSRAM AG
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
85%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1044 granted / 1280 resolved
+13.6% vs TC avg
Minimal +4% lift
Without
With
+3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
48 currently pending
Career history
1328
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.2%
+14.2% vs TC avg
§102
25.3%
-14.7% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1280 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 38-40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishizono et al. (Nishizono) (JP 2009135192 A) or Noda (JP 2020104048 A). In regards to claim 38, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses a method for processing an optoelectronic device (Figs. 1-3), the method comprising: providing a growth substrate (items 20, 30); depositing a first doped layer stack (items 22, 40) on the growth substrate (items 20, 30); mesa-structuring the first doped layer stack (items 22, 40) to provide a top portion surrounded by an inclined sidewall (sidewalls shown) having an angle of less than 90 (10 to 80 degrees); depositing a quantum well structure (item 32) on the mesa-structured first doped layer (item 31) such that a thickness of the quantum well structure (item 32) on the inclined sidewall is smaller than a thickness of the quantum well structure (item 32) on the top portion; depositing a second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) on the quantum well structure (item 32); depositing a structured mask on the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35); and mesa structuring the optoelectronic device as to provide sidewalls thereof exposing edge portions of the quantum well structure (item 32) on the inclined surface, wherein depositing the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) comprises: depositing a third mask layer on top of the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35), structuring the third mask layer such that areas of the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) surrounding in projection the top portion are diffusing the deposited exposed, diffusing a p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) into exposed areas such that the p-type dopant causes a QWI within the quantum well structure (item 32) on the inclined sidewall. Examiner takes the position the method steps are implicit from the resulting product features explicitly disclosed in paragraphs 31-59. In regards to claim 39, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein depositing the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) comprises: depositing a third mask layer on top of the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35), structuring the third mask layer such that areas of the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) surrounding in projection the top portion are diffusing the deposited exposed, and diffusing a p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) into exposed areas such that the p-type dopant causes a QWI within the quantum well structure (item 32) on the inclined sidewall. Examiner takes the position the method steps are implicit from the resulting product features explicitly disclosed in paragraphs 31-59. In regards to claim 40, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein the diffusing comprises: depositing the p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) onto the exposed areas at a first temperature (750 degrees), and diffusing the deposited p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) into the exposed areas at a second temperature (820 or 850 degrees), the second temperature (820 or 850 degrees) being optionally higher than the first temperature (750 degrees). Claim(s) 38 and 39 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noda (JP 2020104048 A). In regards to claim 38, Noda (paragraphs 1-109, Figs. 1-3, 6, 7 and associated text and items, see written opinion filed 12/18/2023) discloses a method for processing an optoelectronic device (Figs. 1-3, 6, 7), the method comprising: providing a growth substrate (item 10); depositing a first doped layer stack (item 32 plus 34 plus 36) on the growth substrate (item 10); mesa-structuring the first doped layer stack (item 32 plus 34 plus 36) to provide a top portion (items 4a-4d) surrounded by an inclined sidewall (items 2a-2d) having an angle of less than 90; depositing a quantum well structure (item 34) on the mesa-structured first doped layer (item 32) such that a thickness of the quantum well structure (item 34) on the inclined sidewall is smaller than a thickness of the quantum well structure (item 34) on the top portion; depositing a second doped layer stack (item 36) on the quantum well structure (item 34); depositing a structured mask on the second doped layer stack (item 36); and mesa structuring the optoelectronic device (Figs. 1-3, 6, 7) as to provide sidewalls thereof exposing edge portions of the quantum well structure (item 32) on the inclined surface, wherein depositing the second doped layer stack (item 36) comprises: depositing a third mask layer on top of the second doped layer stack (item 36), structuring the third mask layer such that areas of the second doped layer stack (item 36) surrounding in projection the top portion are diffusing the deposited exposed, diffusing a p-type dopant (item 36, p-type GaN) into exposed areas such that the p-type dopant causes a QWI within the quantum well structure (item 34) on the inclined sidewall (items 2a-2d). Examiner takes the position the method steps are implicit from the resulting product features. In regards to claim 39, Noda (paragraphs 1-109, Figs. 1-3, 6, 7 and associated text and items, see written opinion filed 12/18/2023) discloses wherein depositing the second doped layer stack (item 36) comprises: depositing a third mask layer on top of the second doped layer stack (item 36), structuring the third mask layer such that areas of the second doped layer stack (item 36) surrounding in projection the top portion are diffusing the deposited exposed, and diffusing a p-type dopant (item 36) into exposed areas such that the p-type dopant causes a QWI within the quantum well structure (item 34) on the inclined sidewall. Examiner takes the position the method steps are implicit from the resulting product features. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 22-27 and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dimitropoulos et al. (Dimitropoulos) (US 2021/0020806 A1 now US 11,201,265 B1) as evidence by and/or in view of Boss et al. (Boss) (WO 2020/216549 A1), Raring et al. (Raring) (US 8,451,876 B1), Feix (102019126506 A1) or Ebbecke (US 2024/0250207 A1). In regard to claim 22, Dimitropoulos (paragraphs 37-146, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses an optoelectronic device (Fig. 9, item 900) comprising: a semiconductor body (item 900) with a layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925), wherein the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925) has a first region (flat region, Fig. 9) and a surrounding second region (sloped sidewall region, Fig. 9) extending to a sidewall of the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925), the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925) comprising: a first n-doped layer (item 910); a quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) arranged on the first n-doped layer (item 910); and a p-doped layer (items 920 or 920 plus 925) arranged on the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935), wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) extends along a lateral plane within the first region (flat region, Fig. 9) of the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925), wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) extends within the second region (sloped sidewall region, Fig. 9) on an inclined surface of one of the n-doped layer (item 910) and p-doped layer (item 920) with regards to the lateral plane to the sidewall of the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925, paragraph 112) such that a thickness of the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) within the second region (sloped sidewall region, Fig. 9) is smaller than a thickness of the quantum well structure (items 915 or 915 plus 935) within the first region (flat region, Fig. 9), and wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) within the second region comprises a p-type dopant (items 920 or 920 plus 925) causing a quantum well intermixing within the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935). The Examiner notes that the Dimitropoulos discloses the Applicant’s claim structure and would intrinsically share the same characteristics in regards to quantum well intermixing Examiner notes that the p-type layers (items 920 or 920 plus 925) would form a p-n junction along the sidewall of quantum well structure. As evidenced by Boss (claims 14, 20, Figs. 1-3 and associated text), quantum well intermixing can occur along flanked structures. As evidenced by Raring (Fig. 2G and associated text), “the gain-peak of the semiconductor material can be spatially manipulated post-growth through quantum well intermixing (QWI) processes and/or disordering of the light emitting layers. A QWI process makes use of the metastable nature of the compositional gradient found at heterointerfaces. The natural tendency for materials to interdiffuse is the basis for the intermixing process. Since the lower energy light emitting quantum well layers are surrounded by higher energy barriers of a different material composition, the interdiffusion of the well-barrier constituent atoms will result in higher energy light emitting layers and therefore a blue-shifted (or shorter) gain peak.” As evidenced by Feix (Figs. 1-8 and associated text), “a local diffusion of impurities and a subsequent mixing of quantum wells, also known as quantum well intermixing, is a possible method to specifically improve the low current behavior of optoelectronic semiconductor chips. This applies in particular to light-emitting diode chips with small dimensions, also referred to as .Math.LEDs, especially with an emission in the red spectral range. Sufficiently long diffusion times must be observed, in particular in a MOVPE reactor, in order to achieve a significant degree of intermixing on a wafer with densely packed .Math.LEDs……. In accordance with at least one embodiment, the at least one intermixing region extends completely through the semiconductor layer sequence in the direction parallel to the growth direction. This means that the mixing area can extend as far as the growth substrate or also into the growth substrate”. Feix (Figs. 1-5) discloses quantum well intermixing along slope regions of the quantum well (item 33). As evidenced by Ebbecke (Abstract, Figs. 1-3 and associated text), quantum well intermixing can occur along sloped regions due to a p-doped material/layer. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Boss, Raring, Feix or Ebbecke for the purpose of changing the band gap (Boss), manipulating the gain-peak (Raring), improve low current behavior of optoelectronics (Feix) or “ to prevent charge carriers from reaching the surface area of a mesa structure defining the device”(Ebbecke). In regard to claims 23, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein a bandgap of the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) in the first region (flat region) is smaller than a bandgap of the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) in the second region (sloped region). In regard to claim 24, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) comprises an intrinsic layer (items 935 or 965) at least in the first region (flat region) adjacent to the n-doped layer (item 910) and/or the p-doped layer (item 920). In regard to claim 25, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein the inclined surface of the n-doped layer (item 910) and/or an area adjacent to the inclined surface of the n-doped layer (item 910) within the second region (sloped region) comprise(s) a larger dopant concentration than a dopant concentration in the first region (flat region) of the n-doped layer (item 910) adjacent to the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935). In regard to claim 26, Dimitropoulos (Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein a p-type dopant (items 920 or 920 plus 925) extends partially into the n-doped layer (item 910) causing a shift of a depletion region towards the n-doped layer (item 910). In regard to claim 35, Dimitropoulos (Figs. 1-4, 5a-5l, 9 and associated text and items) as evidence and/or modified by Boss, Raring, Feix or Ebbecke discloses comprising a p-type dopant (items 920 or 920 plus 925) deposited in the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) within the second region (sloped sidewall region) causing a quantum well intermixing thereof (See rejection of claim 22 above). Claim(s) 27-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dimitropoulos et al. (Dimitropoulos) (US 2021/0020806 A1 now US 11,201,265 B1) as evidence by and/or in view of Park et al. (Park) (KR 101008287 B1). In regard to claim 27, Dimitropoulos (paragraphs 37-146, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses an optoelectronic device (Fig. 9, item 900) comprising: a semiconductor body (item 900) with a layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925), wherein the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925) has a first region (flat region, Fig. 9) and a surrounding second region (sloped sidewall region, Fig. 9) extending to a sidewall of the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925), the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925) comprising: a first n-doped layer (item 910); a quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) arranged on the first n-doped layer (item 910); and a p-doped layer (items 920 or 920 plus 925) arranged on the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935), wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) extends along a lateral plane within the first region (flat region, Fig. 9) of the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925), wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) extends within the second region (sloped sidewall region, Fig. 9) on an inclined surface of one of the n-doped layer (item 910) and p-doped layer (item 920) with regards to the lateral plane to the sidewall of the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925, paragraph 112) such that a thickness of the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) within the second region (sloped sidewall region, Fig. 9) is smaller than a thickness of the quantum well structure (items 915 or 915 plus 935) within the first region (flat region, Fig. 9), but does specifically disclose wherein a doping concentration of the n-doped layer (item 910) in the second region (sloped sidewall region) is lower that a doping concentration in the first region. As evidenced by Park (Abstract, Tech-Solution, Figs. 1-3 and associated text), a doping concentration of a n-doped layer (item 300) in a second region can be lower that a doping concentration in a first region. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Park for the purpose of anisotropic conductivity (Abstract) and/or lower conductivity (claim 1). In regard to claims 28, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein a bandgap of the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) in the first region (flat region) is smaller than a bandgap of the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) in the second region (sloped region). In regard to claims 29, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935, single or multiple quantum well, paragraph 55) comprises a first quantum well (items 915, 915 plus 935 or 965 plus 915 plus 935, single or multiple quantum well, paragraph 55) and a second quantum well (items 915, 915 plus 935 or 965 plus 915 plus 935, single or multiple quantum well, paragraph 55) separated by a quantum well barrier, or wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935, single or multiple quantum well, paragraph 55) comprises a first quantum well (tems 915, 915 plus 935 or 965 plus 915 plus 935, single or multiple quantum well, paragraph 55) arranged between two quantum well barriers. In regard to claims 30, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) comprises an intrinsic layer (items 935 or 965) at least in the first region (flat region) adjacent to the n-doped layer (item 910) and/or the p-doped layer (item 920). In regard to claims 31, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein a thickness of the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) within the second region (sloped sidewall region) is based on an inclination angle between the inclined surface (sloped sidewall region) and the lateral plane (flat region). In regard to claims 32, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein a diameter of the inclined surface (sloped sidewall region) parallel to lateral plane increases with an increasing distance towards the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935) within the first region (flat region). In regard to claims 33, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein the inclined surface of the n-doped layer (item 910) and/or an area adjacent to the inclined surface of the n-doped layer (item 910) within the second region (sloped region) comprise(s) a larger dopant concentration than a dopant concentration in the first region (flat region) of the n-doped layer (item 910) adjacent to the quantum well structure (items 915, 915 plus 935 or 965 plus 915 plus 935). In regard to claims 34, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein the sidewall of the layer stack (items 910 plus 965 plus 915 plus 935 plus 920 plus 925) comprises a mesa structure. In regard to claims 36, Dimitropoulos (paragraphs 64-66, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein a p-type dopant (item 920) extends partially into the n-doped layer (item 910) causing a shift of a depletion region towards the n-doped layer (item 910). In regard to claims 37, Dimitropoulos (paragraphs 55-58, Figs. 1-4, 5a-5l, 9 and associated text and items) discloses wherein the n-doped layer (item 910) and/or the p-doped layer (item 920) comprises a base material selected from the group consisting of GaN, AlGaN, AlGaInP, AlGaInN and AlGaP. Claim(s) 41-50 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishizono et al. (Nishizono) (JP 2009135192 A) as evidence by and/or in view of Park et al. (Park) (KR 101008287 B1) or Noda (JP 2020141048 A). In regards to claim 41, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses method for processing an optoelectronic device, the method comprising: providing a growth substrate(items 20, 30); depositing a first doped layer stack (items 22, 40 or 31 plus 32) on the growth substrate (items 20, 30); mesa-structuring the first doped layer stack (items 22, 40) to provide a top portion surrounded by an inclined sidewall (sidewalls shown) having an angle of less than 90 (10 to 80 degrees); depositing a quantum well structure (item 32) on the mesa-structured first doped layer (item 31) such that a thickness of the quantum well structure (item 32) on the inclined sidewall is smaller than a thickness of the quantum well structure (item 32) on the top portion; depositing a second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) on the quantum well structure (item 32); depositing a structured mask on the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35); and mesa structuring the optoelectronic device as to provide sidewalls thereof exposing edge portions of the quantum well structure (item 32) on the inclined surface. Examiner takes the position the method steps are implicit from the resulting product features explicitly disclosed in paragraphs 31-59. Nishizono does not specifically disclose wherein a doping concentration of the first doped layer (item 31) below the inclined sidewalls is smaller than a doping concentration of the first doped layer (item 31) below the top portion. As evidenced by Park (Abstract, Tech-Solution, Figs. 1-3 and associated text), a doping concentration of a n-doped layer (item 300) in a second region can be lower that a doping concentration in a first region. As evidenced by Noda (Abstract, Tech-Solution, Figs. 1-3 and associated text), a doping concentration of the first doped layer (item 341) below the inclined sidewalls (item 341b) can be smaller than a doping concentration of the first doped layer (item 31) below the top portion (item 341a). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Park or Noda for the purpose of anisotropic conductivity (Abstract) and/or lower conductivity (claim 1). In regards to claim 42, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein mesa-structuring the first doped layer stack ((items 22, 40 or 31 plus 32) comprises: depositing a first mask layer on the first doped layer stack (items 22, 40 or 31 plus 32), structuring the first mask layer such that areas of the first doped layer stack (items 22, 40 or 31 plus 32) surrounding the top portion are exposed, and removing material in exposed areas to form the inclined surface. In regards to claim 43, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein depositing the structured mask on the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) comprises: depositing a second mask layer on the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35), structuring the second mask layer such that areas of the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35), which in projection surrounds the top portion and areas surrounding the top portion are exposed, and removing material in exposed areas. In regards to claim 44, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein the depositing the first doped layer stack (items 22, 40 or 31 plus 32) or the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) comprises depositing a semiconductor base material using MOCVD or MOVPE processes (MOVPE apparatus) with respective different dopant concentrations. In regards to claim 45, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein depositing the first doped layer stack (items 22, 40 or 31 plus 32) and/or the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) comprises depositing an intrinsic layer (item 33) of a base material (GaN) of the respective first and/or second doped layer stack (items 31 plus 32 or items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35), the intrinsic layer being adjacent to the quantum well structure (item 32). In regards to claim 46, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein depositing the quantum well structure (item 32, multiple quantum well structure) comprises depositing one or more quantum layers between respective quantum well barrier layers, the quantum well barrier layers having a larger bandgap than the quantum well layers. In regards to claim 47, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein a thickness of the quantum well layer structure (item 32) is based on the inclination angle between the sidewalls of the first doped layer stack (items 22, 40 or 31 plus 32) and a top planar surface of the first doped layer stack (items 22, 40 or 31 plus 32). In regards to claim 48, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein an angle between the sidewalls of the optoelectronic device (Fig. 1 or 2) and the top surface of the first doped layer stack (items 22, 40 or 31 plus 32) is larger than an angle between the inclined sidewalls of the first doped layer stack (items 22, 40 or 31 plus 32) and the top surface of the first doped layer stack (items 22, 40 or 31 plus 32). In regards to claim 49, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein depositing the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) comprises: depositing a third mask layer on top of the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35), structuring the third mask layer such that areas of the second doped layer stack (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) surrounding in projection the top portion are diffusing the deposited exposed, and diffusing a p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) into exposed areas such that the p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) causes a QWI within the quantum well structure (item 32) on the inclined sidewall. In regards to claim 50, Nishizono (paragraphs 1-64, Figs. 1-3 and associated text and items, see written opinion filed 12/18/2023) discloses wherein the diffusing comprises: depositing the p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) onto the exposed areas at a first temperature (750 degrees), and diffusing the deposited p-type dopant (items, 33, 34, 35, 33 plus 34 or 33 plus 34 plus 35) into the exposed areas at a second temperature (820 or 850 degrees), the second temperature (820 or 850 degrees) being optionally higher than the first temperature (item 750 degrees). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TELLY D. GREEN Examiner Art Unit 2898 /TELLY D GREEN/Primary Examiner, Art Unit 2898 March 2, 2026
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Prosecution Timeline

Dec 18, 2023
Application Filed
Mar 02, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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1-2
Expected OA Rounds
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2y 5m
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