CTFR 18/571,672 CTFR 86836 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This office action is in response to applicant’s arguments/remarks and amendments filed on 05/12/2026. Claims 1, 14, and 27 have been amended. Claims 18-26, and 30 have been previously cancelled. No Claims have been newly added. Accordingly, claims 1-17 and 27-29 are currently pending. Response to Arguments 07-38-02 AIA Applicant’s arguments, see applicant’s arguments/remarks , filed on 05/12/2026 , with respect to the rejection(s) of claim(s) 1, 3-14, 16-17, and 27-29 under 35 U.S.C. 103 as being unpatentable over Lee in view of Weiss have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee, Weiss, and Vo et al US 2014/0312483 A1 as detailed below . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1, 3-14, 16-17, and 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al US 2018/0039324 A1 (hence Lee) in view of Weiss et al US 2013/0070514 A1 (hence Weiss) and Vo et al US 2014/0312483 A1 (hence Vo) . In re claims 1, 14, and 27, Lee discloses a controller coupled to a plurality of hardware modules is arranged for determining activities of at least two of the hardware modules in real time, and determining a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules (Abstract) and teaches the following: An apparatus comprising: memory to store initialization information for a plurality of circuits; and processing circuitry, coupled with the memory, to: retrieve the initialization information from the memory, wherein the initialization information includes an indication of a target die temperature (Paragraph 0019), a target pass rate (Paragraph 0022), and a target throughput (Paragraph 0022); adjust an average die temperature of the plurality of circuits based on the target die temperature; adjust a frequency of the plurality of circuits based on the target pass rate and the target throughput; and adjust a voltage supplied to the plurality of circuits (Paragraphs 0024-0026) However, Lee doesn’t explicitly teach the following: initialization information for a plurality of application-specific integrated circuits (ASICs) wherein the ASICs include multiple ASIC stacks each comprising one or more parallel-connected ASICs, wherein the ASIC stacks are coupled together in series between the supplied voltage Nevertheless, Weiss discloses an integrated circuit employs a plurality of functional blocks, such as but not limited to, processors (e.g., cores) (Abstract) and teaches the following: initialization information for a plurality of application-specific integrated circuits (ASICs) (Paragraphs 0004, 0015, and claim 1) It would have been obvious to one having ordinary skills in the art at the time the invention was filed to have modified the Lee reference to include a plurality of functional blocks, such as but not limited to, processors (e.g., cores), and an on-die distributed programmable passive variable resistance memory array configured to provide configuration information for each of the plurality of functional blocks, as taught by Weiss, with a reasonable expectation of success, in order to allow dynamic changing of hardware configuration of the functional blocks both during normal operation and prior to die packaging (Weiss, Abstract). Nevertheless, Vo discloses a semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via and interposer and teaches the following: wherein the ASICs include multiple ASIC stacks each comprising one or more parallel-connected ASICs, wherein the ASIC stacks are coupled together in series between the supplied voltage (Fig.1, #102, #104, #106, and #108, and Paragraph 0019 “four IC dice are shown, it will be appreciated that a package may include more or fewer IC dice depending on application requirements”, Paragraph 0021 “the IC dice may be different application specific integrated circuit (ASICs) dice”, Fig.2, and Paragraph 0026 “Daughter IC dice 232 and 234 have integrated circuitry layers 236 and 238, respectively”) It would have been obvious to one having ordinary skills in the art at the time the invention was filed to have modified the Lee reference to include integrated circuit (ASICs) dice, as taught by Vo, with a reasonable expectation of success, in order to provide multi-die semiconductor packages having dice with different clock speed ratings (Vo, Paragraph 0001). In re claims 3 and 16, Lee teaches the following: wherein adjusting the frequency of the plurality of ASICs includes performing a coarse frequency tuning procedure, and wherein the processing circuitry is further to perform a fine frequency tuning procedure on the plurality of ASICs subsequent to the coarse frequency tuning procedure (Paragraph 0005) In re claims 4 and 17, Lee teaches the following: wherein the coarse frequency tuning procedure includes adjusting the frequency of the plurality of ASICs by a first adjustment step, and wherein the fine frequency tuning procedure includes adjusting the frequency of the plurality of ASICs by a second adjustment step that is less than the first adjustment step (Paragraph 0005) In re claim 5, Lee teaches the following: wherein the coarse frequency tuning procedure includes determining a pass rate associated with a known job for an ASIC from the plurality of ASICs, and adjusting the frequency of the plurality of ASICs based on a comparison of the determined pass rate to the target pass rate (Paragraphs 0005, and 0017) In re claim 6, Lee teaches the following: wherein the coarse frequency tuning procedure includes: determining that an overall throughput for the plurality of ASICs is lower than the target throughput; and determining a frequency adjustment value to achieve the target throughput (Paragraph 0006) In re claim 7, Lee teaches the following: wherein the determined frequency adjustment value is lower than the second adjust step, and wherein the processing circuitry is further to increase the voltage supplied to the plurality of ASICs to achieve the target throughput (Paragraph 0030) In re claim 8, Lee teaches the following: wherein adjusting the voltage supplied to the plurality of ASICs includes determining an average pass rate associated with a known job for the plurality of ASICs and adjusting the voltage supplied to the plurality of ASICs based on a comparison of the determined average pass rate to the target pass rate (Paragraphs 0029-0030) In re claims 9 and 28, Lee teaches the following: wherein adjusting the voltage supplied to the plurality of ASICs includes increasing the voltage supplied to the plurality of ASICs until a voltage associated with a stack of ASICS connected in parallel meets a minimum predetermined voltage (Paragraphs 0029-0030) In re claims 10 and 29, Lee teaches the following: wherein adjusting the voltage supplied to the plurality of ASICs includes assigning respective test jobs to a subset of ASIC engines in the stack to prevent the subset of ASIC engines from idling subsequent to the voltage associated with the stack meeting the minimum predetermined voltage (Paragraphs 0024-0026) In re claims 11 and 12, the combination of Lee and Weiss discloses the claimed invention except for wherein the voltage supplied to the plurality of ASICs is initially about 3000 mV, and wherein the voltage supplied to the plurality of ASICs is increased in increments of about 333 mV, and wherein the minimum predetermined voltage is about 375 mV. It would have been obvious to one having ordinary skill in the art at the time the invention was made to define the range above, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233. In re claim 13, Lee teaches the following: wherein the apparatus comprises a controller coupled to the plurality of ASICs via a communications interface (Paragraph 0017) 07-21-aia AIA Claim (s) 2 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Weiss, and Vo, and further in view of Kennedy et al US 2021/0333849 A1 (hence Kennedy) . In re claims 2 and 15, the combination of Lee, Weiss, and Vo discloses the claimed invention as recited above but doesn’t explicitly teach the following: wherein adjusting the average die temperature of the plurality of ASICs includes dynamically adjusting a speed of one or more fans Nevertheless, Kennedy discloses handling systems utilizing fans at different speeds (Abstract) and teaches the following: wherein adjusting the average die temperature of the plurality of ASICs includes dynamically adjusting a speed of one or more fans (Paragraphs 0046, 0063, and claim 1) It would have been obvious to one having ordinary skills in the art at the time the invention was filed to have modified the Lee reference to include adjusting a speed of one or more fans, as taught by Kennedy, with a reasonable expectation of success, in order to allow for information handling systems to be general or configured for a specific user or specific use (Kennedy, Paragraph 0002). Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAMI KHATIB whose telephone number is (571)270-1165. The examiner can normally be reached M-F: 9:00am-5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Erin M Piateski can be reached at 571-270 7429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAMI KHATIB/Primary Examiner, Art Unit 3669 Application/Control Number: 18/571,672 Page 2 Art Unit: 3669 Application/Control Number: 18/571,672 Page 3 Art Unit: 3669 Application/Control Number: 18/571,672 Page 4 Art Unit: 3669 Application/Control Number: 18/571,672 Page 5 Art Unit: 3669 Application/Control Number: 18/571,672 Page 6 Art Unit: 3669 Application/Control Number: 18/571,672 Page 7 Art Unit: 3669 Application/Control Number: 18/571,672 Page 8 Art Unit: 3669 Application/Control Number: 18/571,672 Page 9 Art Unit: 3669 Application/Control Number: 18/571,672 Page 10 Art Unit: 3669
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