DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 26-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US Patent Application Publication No. 2022/0254784) (“Lee”).
Regarding Claim 26, Lee teaches a memory device comprising: a plurality of memory cells stacked in a vertical direction (see Figure 1B); wherein each of the plurality of memory cells includes a transistor (Figure 1B, items 130 and ¶0046) and a capacitor (Figure 1B, items 127 and ¶0047) electrically connected to the transistor in a lateral direction, wherein the transistor includes a channel material layer (Figure 1B, item 125), a word line (Figure 1B, item 107 and Figure 3B, item 307) surrounding the channel material layer, and a gate insulating layer (Figure 3B, item 304) disposed therebetween, wherein the capacitor includes an electrode member electrically connected to the transistor, a dielectric layer disposed on a surface of the electrode member, and a plate electrode disposed on a surface of the dielectric layer (note all elements are inherent in the existence of a capacitor structure as every capacitor has a dielectric between two conductive plates, see Figures 1B and 3B with ¶0047, with specific structure of the horizontally oriented capacitors shown in Figure 18B and described in ¶0204), a bit line (Figure 1B, item 103-1) connected to a plurality of transistors of the plurality of memory cells, and extending in a vertical direction (see Figure 1B) is provided; a body insulating layer (¶0054) surrounding at least a portion of an outer surface of the bit line between the bit line and the word line is provided; and a filling insulating layer (¶0054) which is a separate material layer (note the layers are separated vertically into different portions of the device – this language does not require different materials to be present) from the body insulating layer is provided between two mutually adjacent word lines of the plurality of transistors.
Regarding Claim 27, Lee further teaches the transistor has a gate-all-around (GAA) structure (see Figure 3B).
Regarding Claim 28, Lee further teaches the body insulating layer has a line shape extending in the same direction as the word line when observed from above (¶0054 – note if viewed from above, space between items 107-1 filled with insulating layer would have a “line shape” in the same manner as the word lines themselves).
Regarding Claim 29, Lee further teaches an insertion insulating layer (¶0054) surrounding a portion of the gate insulating layer adjacent to the electrode member and extending to cover a side surface of the word line, wherein the insertion insulating layer is a separate material layer from the body insulating layer and the filling insulating layer (note the layers are separated vertically and horizontally into different portions of the device – this language does not require different materials to be present).
Regarding Claim 30, Lee further teaches the body insulating layer is in contact with a first side surface of the filling insulating layer, wherein the insertion insulating layer is in contact with a second side surface of the filling insulating layer (note the insulating layer described in ¶0054 can be broken into a body insulating layer, filling insulating layer, and insertion insulating layer as no physical differences in any of the layers have been required by the current claim language).
Regarding Claim 31, the language "the insertion insulating layer is an atomic layer deposition (ALD) material layer," is directed towards the process of making an insulating layer. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "the insertion insulating layer is an atomic layer deposition (ALD) material layer" only requires an insulating later, which does not distinguish the invention from Lee, who teaches the structure as claimed.
Allowable Subject Matter
Claims 1-25 are allowed.
The following is an examiner’s statement of reasons for allowance: None of the prior art, alone or in combination, teaches all the limitations of the claims, specifically including but not limited to “forming a first trench in a capacitor formation region adjacent to the transistor formation region of the structure; forming a first recess exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material exposed by the first trench in the capacitor formation region; forming a mold insulating layer filling the first recess; forming a bit line connected to one end of the channel material layer in a region corresponding to the second vertical hole in the transistor formation region; and forming a second recess by removing the channel material layer and the gate insulating material layer from the capacitor formation region, forming an electrode member connected to the other end of the channel material layer on an inner surface of the second recess, and forming a capacitor including the electrode member, a dielectric layer, and a plate electrode by sequentially forming the dielectric layer and the plate electrode on the electrode member” of Claim 1 and “forming a second vertical hole in a region corresponding to the first vertical hole in the structure where the gate insulating material layer and the dummy channel material layer are formed; exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material from a transistor formation region around the second vertical hole of the structure; forming a word line surrounding the exposed portion of the gate insulating material layer in the transistor formation region; forming a first trench in a capacitor formation region adjacent to the transistor formation region of the structure; forming a first recess exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material exposed by the first trench in the capacitor formation region; forming a mold insulating layer filling the first recess; forming a second recess by removing the dummy channel material layer and the gate insulating material layer from the capacitor formation region, forming an electrode member on an inner surface of the second recess, forming a capacitor including the electrode member, a dielectric layer, and a plate electrode by sequentially forming the dielectric layer and the plate electrode on the electrode member; forming an empty channel space by removing the dummy channel material layer from the transistor formation region, and forming a channel material layer connected to the capacitor in the empty channel space to define a transistor including the channel material layer; and forming a bit line connected to the channel material layer” of Claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Saeedi Vahdat et al. (US Patent No. 11,227,864)
Karda et al. (US Patent Application Publication No. 2022/0278105)
Karda et al. (US Patent Application Publication No. 2022/0149046)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891