Prosecution Insights
Last updated: April 19, 2026
Application No. 18/572,369

Printed Circuit Board And Method For Soldering A Chip Housing In A Process-Reliable Manner

Final Rejection §102
Filed
Dec 20, 2023
Examiner
EGOAVIL, GUILLERMO J
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lisa Dräxlmaier GmbH
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
574 granted / 640 resolved
+21.7% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
664
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.0%
+4.0% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102
DETAILED ACTION This Office Action is in response to a Non-Final, filed 02/26/2026, on the application that was filed on 12/20/2023. Claims 1-3 are presented for examination consideration. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings Applicant’s Drawing and Specification Amendments (filed on 02/26/2026) are persuasive in resolving the following structural inconsistencies to support the claims: Fig. 1 of the Amended Drawings shows the limitation phrase “rear metallic mating surface” claimed in independent claim 1 with written support in ¶[0034] of the Amended Specification. The drawing objections cited in the last office action (mailed on 08/27/2025) is withdrawn. Response to Arguments and Amendments Applicant's Claim Amendments (filed on 02/26/2026) with respect to the 112(b) rejection of claim 2 that was cited in the office action (mailed on 08/27/2025) is persuasive due to amending the claim to particularly point out and distinctly claim the subject matter. The amendment resolved the indefinite limitation FROM “wherein the partial surfaces are arranged in a grid-like distribution over the cooling surface” TO “wherein the partial surfaces are arranged in a grid-like distribution dividing the cooling surface”. The 112(b) rejection of claim 2 is withdrawn. Applicant's Claim Amendments (filed on 02/26/2026) with respect to the 112(b) rejection of claim 3 that was cited in the office action (mailed on 08/27/2025) is persuasive due to amending the claim to particularly point out and distinctly claim the subject matter. The amendment resolved the indefinite limitation FROM “wherein the vias are arranged distributed in a grid-like manner over the cooling surface” TO “wherein the vias are arranged distributed in a grid-like manner enclosed within the cooling surface”. The 112(b) rejection of claim 3 is withdrawn. However, Applicant’s Arguments/Remarks filed on 02/26/2026 with respect to the 35 USC § 102 rejection of independent claim 1 has been fully considered but it is not persuasive. Applicant’s basis of arguments on pages 6-8 is “Delheimer does not anticipate the claimed invention because Delheimer's core teaching is functionally opposite to the claimed solder-flow regime”. Specifically, Applicant’s argument indicates “present claims require open vias that cooperate with a rear metallic mating surface such that excess solder is intentionally allowed to pass through the vias and spread on the rear surface during reflow, as part of achieving a process-reliable, low-void large-area thermal joint” (as indicated in ¶[0011 & 0019-0020]). Applicant continues to argue “Delheimer, by contrast, explicitly teaches that solder entering vias is undesirable and must be prevented, stating that “loss of solder through the vias during reflow can cause the package to collapse” and therefore teaching solder mask structures that “prevent the molten solder from wicking into and potentially blocking the vias”” (as indicated by Delheimer in ¶[0007 & 0020] NOT ¶[0007 & 0021]). Therefore, according to the Applicant, “Delheimer does not disclose the claimed subject matter arranged as required by the claims and, moreover, teaches away from the functional solder-flow behavior that is central to the present invention”. There is NO evidence that the Applicant presented in the arguments that the mapping, based on the reference of Delheimer, of the limitation structures in independent claim 1 by the Examiner is or should be traversed. Though, the intent of the application invention, as outline in the disclosure, maybe opposite to the reference of Delheimer, the corresponding mapping of limitation structures of independent claim 1 to Delheimer is proper in the rejection. Consequently, the “claims are not to be read in a vacuum, and limitations therein are to be interpreted in light of the specification, giving the claim limitations their broadest reasonable interpretation”, in accordance to MPEP § 2111, and NOT to import the claim limitations FROM the specification, according to MPEP § 2111.01 II. The arguments presented by the Applicant’s Argument is FROM the Applicant’s Specification and NOT the scope of the structural limitations in claim 1. Therefore, the arguments that the Applicant presented are based on wanting the structures and intent of the specification and the Figures to be read into the claim limitations instead of reading the claims in light of the specification and the claimed structure, which is impermissible. Therefore, the Applicant's arguments to the 102 rejection of independent claim 1 is moot. The 102 rejection of claim 1 will not be withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Delheimer (US 20030234441 A1 and Delheimer hereinafter). Regarding claim 1, Delheimer discloses a printed circuit board configured for process-reliable soldering of a chip package (items 12, 30 of Fig. 7 & item 12 of Figs. 5-6 and ¶[0017-0020] shows and indicates printed circuit board 12 {substrate 12} configured for process-reliable soldering of chip package 30 {MLF package 30}), the printed circuit board comprising: a metallic cooling surface, a multiplicity of metallic contact surfaces surrounding the cooling surface, and a rear metallic mating surface on a side opposite the cooling surface (items 14, 16 of Figs. 5-6 and ¶[0017-0019] shows and indicates printed circuit board 12 is comprised of metallic cooling surface 14-front {front surface of Cu thermal pad 14 located on the top surface of substrate 12}, multiplicity of metallic contact surfaces 16 {Cu I/O pads 16} surrounding cooling surface 14-front, and rear metallic mating surface 14-rear {rear surface of Cu thermal pad 14 located on the lower surface of substrate 12} on the side opposite cooling surface 14-front), wherein the mating surface is connected to the cooling surface by open vias (item 18 of Figs. 5-7 and ¶[0017-0020] shows and indicates where mating surface 14-rear is connected to cooling surface 14-front by open vias 18), and lanes of solder resist are arranged on the cooling surface, which lanes both divide the cooling surface into a plurality of partial surfaces and enclose the vias (item 20, 22, 21 of Fig. 5 and ¶[0018] shows and indicates lanes 22_21 {mask 20 forming rectilinear portions 22 and annular-shaped portions 21} of solder resist 20 are arranged on cooling surface 14-front, which lanes 22_21 both divide cooling surface 14-front into the plurality of partial surfaces 14-grids {thermal pad 14 divided into grids by solder mask 20} and enclose vias 18). Regarding claim 2, Delheimer discloses a printed circuit board, wherein the partial surfaces are arranged in a grid-like distribution dividing the cooling surface (Fig. 5 and ¶[0018] shows and indicates where partial surfaces 14-grids are arranged in a grid-like distribution dividing cooling surface 14-front, synonymous to Applicant’s disclosure in Fig. 1 and ¶[0034] of the PgPub). Regarding claim 3, Delheimer discloses a printed circuit board, wherein the vias are arranged distributed in a grid-like manner enclosed within the cooling surface (Fig. 5 and ¶[0018] shows and indicates where vias 18 are arranged distributed in a grid-like manner enclosed within cooling surface 14-front, synonymous to Applicant’s disclosure in Fig. 1 and ¶[0034] of the PgPub). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUILLERMO J EGOAVIL/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Aug 24, 2025
Non-Final Rejection — §102
Feb 26, 2026
Response Filed
Mar 04, 2026
Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+8.5%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allow rate.

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