Prosecution Insights
Last updated: August 16, 2026
Application No. 18/572,699

OPTOELECTRONIC SEMICONDUCTOR DEVICE, ARRAY OF OPTOELECTRONIC SEMICONDUCTOR DEVICES AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Dec 20, 2023
Priority
Jul 02, 2021 — DE 10 2021 117 123.7 +1 more
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ams-osram AG
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
694 granted / 814 resolved
+17.3% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
16 currently pending
Career history
826
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.4%
+22.4% vs TC avg
§102
33.0%
-7.0% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 814 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 21-23, 25, 26, 28, 29 and 39 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Varghese et al. US 2021/0226090 A1. Regarding claims 21-23, 25, 26, 28 and 29, Varghese discloses: A method for manufacturing an optoelectronic semiconductor device (Figs. 2-4), the method comprising: forming a semiconductor layer stack (11) comprising an active zone (13) for generating or receiving electromagnetic radiation (Figs. 2A/2B); thereafter, forming a hard mask layer (21) over the semiconductor layer stack (Figs. 2A/2B); thereafter, patterning the hard mask layer to form a hard mask having a width d measured in a first lateral direction; thereafter, patterning the semiconductor layer stack to form a mesa having a width W measured in the first lateral direction with d > w, wherein the hard mask protrudes from the mesa at a first lateral end and at a second lateral end of the mesa, and wherein the first lateral end and the second lateral end are arranged at opposing sides of the mesa along the first lateral direction (Fig. 2C); thereafter, forming a cover layer (16) over sidewalls of the mesa, the cover layer comprising a semiconductor material (Fig. 2E); and thereafter, etching the semiconductor material of the cover layer using the hard mask as an etching mask to form a separating groove (Fig. 4A/4B, separation through 16). (claim 22) Fig. 2B para 0064; Fig. 2C para 0066. (claim 23) Figs. 2A/2B; 12/13/14). (claim 25) para 0056. (claim 26) Fig. 4A. (claim 28) Figs. 4A/4B. (claim 29) Figs. 4A/4B. Regarding claim 39, Varghese discloses: An array of optoelectronic semiconductor devices (Figs. 2-4) comprising: a semiconductor layer stack (11) comprising an active zone (13) configured to generate or receive electromagnetic radiation, the semiconductor layer stack being patterned to form a plurality of mesas having a width W measured in a first lateral direction (Figs. 2A/2B); portions of a hard mask (21) arranged over the semiconductor layer stack and having a width d measured in the first lateral direction, with d > w, wherein the hard mask protrudes from each of the mesas at a first lateral end and at a second lateral end of each of the mesas, and wherein the first lateral end and the second lateral end are arranged at opposing sides of the mesas along the first lateral direction (Fig. 2C); a cover layer (16) arranged over sidewalls of each of the mesas, the cover layer comprising a semiconductor material (para 0068) (Fig. 2E); and a plurality of separating grooves (Figs. 4A/4B; separation through 16) between adjacent optoelectronic semiconductor devices, wherein the separating grooves extend between the portions of the hard mask of adjacent optoelectronic semiconductor devices and are directly adjacent to the portions of the hard mask of the adjacent optoelectronic semiconductor devices. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 24, 30, 31, 33, 34 and 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Varghese et al. US 2021/0226090 A1. Regarding claim 24, although Varghese does not specifically disclose “wherein forming the hard mask layer comprises forming a conductive layer directly adjacent to the second semiconductor layer of the semiconductor layer stack”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the hard mask 21 of Varghese, in para 0056, to be made of a conductive material as well as the dielectric noted since such a material would suffice as a hard mask as well when etching the semiconductor layer stack. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Lesbin, 125 USPQ 416. Regarding claims 30, 31, 33, 34 and 38, Varghese discloses: An optoelectronic semiconductor device (Fig. 2-4) comprising: a semiconductor layer stack (11) comprising an active zone (13) configured to generate or receive electromagnetic radiation, the semiconductor layer stack being patterned to form a mesa having a width W measured in a first lateral direction (Fig. 2B); a hard mask (21) arranged over the semiconductor layer stack and having a width d measured in the first lateral direction, with d > W, wherein the hard mask protrudes from the mesa at a first lateral end and at a second lateral end of the mesa, wherein the first lateral end and the second lateral end are arranged at opposing sides of the mesa along the first lateral direction, and wherein the hard mask is directly adjacent to a semiconductor layer (14) of the semiconductor layer stack (Fig. 2C); and a cover layer (16) arranged over sidewalls of the mesa, the cover layer comprising a semiconductor material (para 0068). Although Varghese does not specifically disclose “wherein the hard mask layer comprises a conductive layer”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the hard mask 21 of Varghese, in para 0056, to be made of a conductive material as well as the dielectric noted since such a material would suffice as a hard mask as well when etching the semiconductor layer stack. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Lesbin, 125 USPQ 416. (claim 31) para 0056. (claim 33) para 0068. (claim 34) Figs. 2A/2B; 12/13/14). (claim 38) Figs. 4A/4B. Allowable Subject Matter Claims 27, 32 and 35-37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 27 stating “further comprising forming a passivation layer after forming the separating groove; removing horizontal portions of the passivation layer to expose a surface of the mesas; and forming a conductive material to cover the surface of the mesas”; of claim 32 stating “wherein a width S of the cover layer is equal to at least a difference between d and w, the width S being measured in the first lateral direction”; and of claim 35 stating “wherein the cover layer comprises a first sublayer of the second conductivity type and a second sublayer of the first conductivity type, the first sublayer being directly adjacent to the sidewalls of the mesa”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Dec 20, 2023
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.9%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 814 resolved cases by this examiner. Grant probability derived from career allowance rate.

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