DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In the instant case, Claim 1 discloses “a sense spacer conductor that is electrically connected to the sense terminal, keeps a gap between the first substrate and the second substrate, and is electrically connected to the second conductor plate, from a side close to the first substrate, of the second substrate.”. it is not clear what is meant by “a side close to the first substrate”, since the substrate has multiple sides and edges, the mete and bound of the claim is not defined as to enable one of ordinary skill in the art to identify the claimed limits. Examiner will consider that Claim 1 can mean “from a side close to the first substrate, than the second substrate,” and will read on the claimed limitation.
Applicant correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 7 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horio et al. (US 2017/0077068), (hereinafter, Horio).
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RE Claim 1, Horio discloses in FIGS. 1-9, FIGS. 7a, 8 and 9 are annotated above, a power semiconductor module comprising:
a high potential terminal 18 “external terminal pin”, since it is connected to anode and gate potential, referring to FIGS. 8 and 9;
a first conductor plate 14j “chip mounting pattern” electrically connected to the high potential terminal 18;
a plurality of semiconductor chips “Q1a-Q1d” of which drains “D1” or collectors are connected to the first conductor plate 14j;
a second conductor plate 16b “second metal layer”, referring to FIG. 7b connected to sources “SS1” or emitters of the plurality of semiconductor chips “Q1a-Q1d” and disposed to face the first conductor plate 14j [0091];
a low potential terminal 17b, since it is connected to the cathode, electrically connected to the second conductor plate 16b, referring to FIGS. 6a and 7b [0086];
a sense terminal 21a “external sense terminal” configured to detect potentials of the sources or emitters of the plurality of semiconductor chips “Q1a-Q1d” [0083 and 0089];
a first substrate 3B “insulating substrate” on which the high potential terminal 18, the first conductor plate 14j, and the sense terminal 21a are provided;
a second substrate 5 “printed circuit board” disposed to face the first substrate 3B and provided with the second conductor plate 16b; and
a sense spacer conductor “lower portion of conductor pillar 21a”, referring to FIG. 9 that is electrically connected to the sense terminal 21a, keeps a gap between the first substrate 3B and the second substrate 5, which is implicitly met, and is electrically connected to the second conductor plate 16b, referring to FIG. 7b. It is the examiner position that the connection is achieved via source line 16s and a second layer 16w [0096 and 0105], hence meeting the claimed limitation, from a side close to the first substrate 3B, than the second substrate 5, referring to FIG. 9, referring to the USC 112 rejection above;
wherein the sense spacer conductor “lower portion of the conductor 21a”, which is single, corresponds to the plurality of semiconductor chips “Q1a-Q1d”, referring to FIG. 9,
the high potential terminal 18 is provided at a first side “lower substrate edge” of the first substrate 3B, referring to FIGS. 6a and 9,
the sense spacer conductor “lower portion of the conductor 21a and the plurality of semiconductor chips “Q1a-Q1d” are disposed on a same portion of the first side, referring to FIG. 6a, and
a shortest distance between the sense spacer conductor “lower portion of the conductor 21a” and the first side is smaller than a shortest distance between a semiconductor chip “Q1c and Q1d” closest to the high potential terminal 18.
RE Claim 2, Horio discloses power semiconductor module, further comprising:
a first insulating substrate as the first substrate 3B, referring to Claim 1 rejection, on one of which main surfaces the first conductor plate 14j is disposed; and
a second insulating substrate as the second substrate 5 on one of which main surfaces the second conductor plate 16b is disposed,
wherein the first insulating substrate 3B and the second insulating substrate 5 are disposed such that the first conductor plate 14j and the second conductor plate 16b face each other, referring to FIGS. 6 and 9,
the sense terminal 21a “external sense terminal” is electrically insulated from the first conductor plate 14j, is disposed on the main surface, on which the first conductor plate 14j is disposed, of the first insulating substrate, and is electrically connected to a third conductor plate 14l “circuit plate” [0082] facing the second conductor plate 16b, referring to FIGS. 6 and 9, and
the sense terminal 21a “external sense terminal” keeps a distance between the third conductor plate 14l “circuit plate” and the second conductor plate 16b, and is connected to the second conductor plate 16b via the sense spacer conductor “lower portion of the conductor 21a” electrically connected to the second conductor plate 16b via the third conductor plate 14l “circuit plate”, referring to FIGS. 6 and 9 [0082].
RE Claim 5, Horio discloses power semiconductor module, wherein in the second conductor plate 16b, a position at which the plurality of semiconductor chips “Q1a-Q1d” are electrically connected is between a position at which the sense spacer conductor “lower portion of the conductor 21a” is electrically connected and a position at which the low potential terminal 17 is electrically connected, referring to FIG. 7b which depicts the lower face of the second substrate 5. Furthermore, the semiconductor chips “Q1a-Q1d” are located between the low potential terminal 17b and the connecting point 16w to the sense spacer “lower portion of conductor 21a”, hence meeting the claimed limitations.
RE Claim 7, Horio discloses power semiconductor module, wherein the sense terminal and a gate terminal 22b, together with the high potential terminal 18, since are connected to the anode of the diode, are provided at the first side of the first substrate 3B “upper side”, together with the gate wiring 16l and 17j, referring to FIGS. 7a, 7b and 9 [0083].
RE Claim 10, Horio discloses a power conversion device [0157] comprising:
a main circuit including one or more pairs of upper, with G1 “first gate connections” and lower arms, with G2 “first gate connections”, referring to FIG. 8 [0085-0087 and 0157]; and
a drive circuit that drives the upper and lower arms. Since the gate has a riving circuit via the sum of inductance Li and Lo as well as the terminals 21a, 21b, 22a and 22b are connected to a driving circuit the limitation is met since the deriving circuitry is a must in order for the power conversion device to operate,
wherein the upper and lower arms include the power semiconductor module according to Claim 1, which includes the semiconductor chips Q1a-Q1d, referring to Claim 1 rejection above.
Allowable Subject Matter
Claims 3, 4, 6, 8 and 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. NAGASAKI et al. (US 2021/0280483) disclose a power semiconductor apparatus includes a power semiconductor element having low and high potential side electrodes and a sense electrode, high and low potential side conductors electrically connected with the high potential side electrodes, respectively, a sense wiring electrically connected with the sense electrode, and a first metal portion facing the low potential side conductor or the low potential side conductor across the sense wiring. When viewed from an array direction of the sense wiring and the first metal portion, the sense wiring has a facing portion facing the high or low potential side conductor, the first metal portion forms a recess in a part overlapping the facing portion, and a depth of the recess is formed such that a distance between a bottom of the recess and the sense wiring is larger than a distance between the sense wiring and the high or low potential side conductor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
(Original) A power semiconductor module comprising:
a high potential terminal; a first conductor plate electrically connected to the high potential terminal;
a plurality of semiconductor chips of which drains or collectors are connected to the first conductor plate;
a second conductor plate connected to sources or emitters of the plurality of semiconductor chips and disposed to face the first conductor plate;
a low potential terminal electrically connected to the second conductor plate;
a sense terminal configured to detect potentials of the sources or emitters of the plurality of semiconductor chips;
a first substrate on which the high potential terminal, the first conductor plate, and the sense terminal are provided;
a second substrate disposed to face the first substrate and provided with the second conductor plate; and
a sense spacer conductor that is electrically connected to the sense terminal, keeps a gap between the first substrate and the second substrate, and is electrically connected to the second conductor plate, from a side close to the first substrate, of the second substrate,
wherein the sense spacer conductor, which is single, corresponds to the plurality of semiconductor chips,
the high potential terminal is provided at a first side of the first substrate,
the sense spacer conductor and the plurality of semiconductor chips are disposed on a same portion of the first side, and
a shortest distance between the sense spacer conductor and the first side is smaller than a shortest distance between a semiconductor chip closest to the high potential termina
The power semiconductor module according to claim 1, further comprising:
a first insulating substrate as the first substrate on one of which main surfaces the first conductor plate is disposed; and
a second insulating substrate as the second substrate on one of which main surfaces the second conductor plate is disposed,
wherein the first insulating substrate and the second insulating substrate are disposed such that the first conductor plate and the second conductor plate face each other,
the sense terminal is electrically insulated from the first conductor plate, is disposed on the main surface, on which the first conductor plate is disposed, of the first insulating substrate, and is electrically connected to a third conductor plate facing the second conductor plate, and
the sense terminal keeps a distance between the third conductor plate and the second conductor plate, and is connected to the second conductor plate via the sense spacer conductor electrically connected to the second conductor plate via the third conductor plate.
The power semiconductor module according to claim 2, wherein
the high potential terminal is connected to the first conductor plate at the first side of the first insulating substrate, and
a shortest distance between the sense spacer conductor and the high potential terminal is smaller than a shortest distance between the semiconductor chip closest to the high potential terminal, among the plurality of semiconductor chips, and the high potential terminal.
4. The power semiconductor module according to claim 3, wherein a shortest distance between the sense spacer conductor and the first side is smaller than the shortest distance between the semiconductor chip closest to the high potential terminal, among the plurality of semiconductor chips, and the first side.
5. The power semiconductor module according to claim 1, wherein in the second conductor plate, a position at which the plurality of semiconductor chips are electrically connected is between a position at which the sense spacer conductor is electrically connected and a position at which the low potential terminal is electrically connected.
6. The power semiconductor module according to claim 1, wherein
a planar positional relationship among the high potential terminal, the sense spacer conductor, the plurality of semiconductor chips, and the low potential terminal is that, when viewed from a position where the high potential terminal is electrically connected to the first conductor plate, the sense spacer conductor, the plurality of semiconductor chips, and a position at which the low potential terminal is electrically connected to the second conductor plate are arranged in this order.
7. The power semiconductor module according to claim 1, wherein the sense terminal and a gate terminal, together with the high potential terminal, are provided at the first side of the first substrate.
8. The power semiconductor module according to claim 7, wherein the gate terminal is electrically connected to gate electrodes of the plurality of semiconductor chips via a first gate wiring conductor plate group and a plurality of bonding wires, the first gate wiring conductor plate group including a plurality of conductor plates disposed on the main surface, on which the first conductor plate is disposed, of the first substrate.
9. The power semiconductor module according to claim 7, wherein
a gate drive voltage provided from the gate terminal is provided to a gate electrode of each of the plurality of semiconductor chips at a different voltage level,
when a gate current flows into the gate electrode of each of the plurality of semiconductor chips, a switching element of a semiconductor close to the high potential terminal, among the plurality of semiconductor chips, is given a high voltage level, and a switching element of a semiconductor far from the high potential terminal and close to the low potential terminal, among the plurality of semiconductor chips, is given a low voltage level, and when the gate current flows out of the gate electrode of each of the plurality of semiconductor chips, the switching element of the semiconductor close to the high potential terminal, among the plurality of semiconductor chips, is given a low voltage level, and the switching element of the semiconductor far from the high potential terminal and close to the low potential terminal, among the plurality of semiconductor chips, is given a high voltage level.
10. A power conversion device comprising:
a main circuit including one or more pairs of upper and lower arms; and
a drive circuit that drives the upper and lower arms,
wherein the upper and lower arms include the power semiconductor module according to claim 1.