Prosecution Insights
Last updated: October 02, 2026
Application No. 18/572,960

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

Non-Final OA §103
Filed
Dec 21, 2023
Priority
Sep 28, 2022 — nonprovisional of PCTCN2022122169
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
701 granted / 821 resolved
+17.4% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
26 currently pending
Career history
830
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.3%
+22.3% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0123183 A1 in view of Park et al. US 2019/0025634 A1. Regarding claims 1, Kim discloses: A display substrate, having a plurality of pixels distributed in an array (Fig. 11 in view of Figs. 3-8), wherein the display substrate comprises: a light-emitting substrate (Fig. 11 in view of 8), comprising a base substrate (SUB), a plurality of light-emitting devices (DPL), a plurality of switch elements (PCL) and an encapsulation layer (INS4) which are arranged on the base substrate, wherein the switch element is configured to drive the light-emitting device to emit light, the encapsulation layer encapsulates the light- emitting device, and at least one light-emitting device and at least one switch element are arranged in each pixel correspondingly (Figs. 3-8 and 11); a color conversion layer (CCL), arranged at a side of the encapsulation layer away from the base substrate, wherein the color conversion layer comprises a separation bank (BNK2), a color conversion pattern (CCL) and a leveling layer (LRL); the separation bank comprises a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction, the first direction intersects with the second direction and is parallel to the base substrate; the plurality of first portions and the plurality of second portions intersect with each other to define a plurality of first openings corresponding to the plurality of pixels (para 0162; BNK2 surrounding light emitting areas and pixels) (Fig. 11); and a color filtering layer (CFL), arranged at a side of the color conversion layer away from the base substrate, wherein the color filtering layer comprises a light-shielding pattern (BM) and a color filtering pattern (CF1, CF2, CF3), the light-shielding pattern defines a plurality of second openings corresponding to the plurality of first openings, and the color filtering pattern is arranged in the second opening (Fig. 11). Kim does not disclose: at least one of the first portion and the second portion comprises a light-transmitting bank pattern and a light-shielding bank pattern; the light-transmitting bank pattern is provided with a groove arranged in a direction in which the at least one of the first portion and the second portion extends, the light- shielding bank pattern is filled in the groove; the color conversion pattern is arranged in the first opening, and a first step is between the color conversion pattern and the separation bank in a direction perpendicular to the base substrate, and the leveling layer at least partially fills the first opening to fill the first step and form a flat surface at a side away from the base substrate. Park discloses a publication from a similar field of endeavor in which: at least one of the first portion and the second portion comprises a light-transmitting bank pattern (120) and a light-shielding bank pattern (110); the light-transmitting bank pattern is provided with a groove (120g) arranged in a direction in which the at least one of the first portion and the second portion extends, the light- shielding bank pattern is filled in the groove; the color conversion pattern (320) is arranged in the first opening, and a first step (step shown between 120 and 320) is between the color conversion pattern and the separation bank in a direction perpendicular to the base substrate, and the leveling layer (500) at least partially fills the first opening to fill the first step (Fig. 5). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the configuration of the bank region of Park within the similar structure of Kim such that the leveling layer forms a flat surface at a side away from the base substrate to determine a sufficiently high height light-shielding member thereby further increasing suppression of light leakage defect between adjacent pixels (see Park para 0111-0112). (claim 2) Kim: a buffer layer (Fig. 7; CP capping layer). (claim 3) Kim: a quantum dot material (Fig. 7; QDr quantum dot). (claim 4) Park: Fig. 7; para 0095, width of 110a in X direction greater than width of 110b in the Y direction. (claim 5) Park: Fig. 5; 110 and 120 have the same height such that top surface is flush. (claim 6) Park: Fig. 5; 120 having inner walls slanted with decreasing width from top to bottom. (claim 7) Park: Fig. 9B; 111 is recessed to a lower height than 120. (claim 8) Kim/Park: as in the combination above, Kim’s leveling layer LRL is similar to Park’s Fig. 9B, 500 which fills the recess region 111t. (claim 9) Park: Fig. 9B, regions 111 and 120 shown with slanted/inclined sidewalls. (claim 10) Park: Fig. 9B, regions 111 and 120 shown with same inner angle. (claims 11 and 13) Park: Fig. 9B, outer walls of 120 in contact with light conversion regions 320 and have the same inclination in opposite directions. (claim 12) Kim: Fig. 7, CCL1 shown in a protruding central top surface and a recessed bottom surface. (claim 14) Kim: paras 0072-0073 (claim 15) Park: para 0064 OLED. Regarding claim 16, Kim discloses: A display device, comprising a display substrate (Fig. 3), the display substrate, having a plurality of pixels distributed in an array (Fig. 11 in view of Figs. 3-8), wherein the display substrate comprises: a light-emitting substrate (Fig. 11 in view of 8), comprising a base substrate (SUB), a plurality of light-emitting devices (DPL), a plurality of switch elements (PCL) and an encapsulation layer (INS4) which are arranged on the base substrate, wherein the switch element is configured to drive the light-emitting device to emit light, the encapsulation layer encapsulates the light- emitting device, and at least one light-emitting device and at least one switch element are arranged in each pixel correspondingly (Figs. 3-8 and 11); a color conversion layer (CCL), arranged at a side of the encapsulation layer away from the base substrate, wherein the color conversion layer comprises a separation bank (BNK2), a color conversion pattern (CCL) and a leveling layer (LRL); the separation bank comprises a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction, the first direction intersects with the second direction and is parallel to the base substrate; the plurality of first portions and the plurality of second portions intersect with each other to define a plurality of first openings corresponding to the plurality of pixels (para 0162; BNK2 surrounding light emitting areas and pixels) (Fig. 11); and a color filtering layer (CFL), arranged at a side of the color conversion layer away from the base substrate, wherein the color filtering layer comprises a light-shielding pattern (BM) and a color filtering pattern (CF1, CF2, CF3), the light-shielding pattern defines a plurality of second openings corresponding to the plurality of first openings, and the color filtering pattern is arranged in the second opening (Fig. 11). Kim does not disclose: at least one of the first portion and the second portion comprises a light-transmitting bank pattern and a light-shielding bank pattern; the light-transmitting bank pattern is provided with a groove arranged in a direction in which the at least one of the first portion and the second portion extends, the light- shielding bank pattern is filled in the groove; the color conversion pattern is arranged in the first opening, and a first step is between the color conversion pattern and the separation bank in a direction perpendicular to the base substrate, and the leveling layer at least partially fills the first opening to fill the first step and form a flat surface at a side away from the base substrate. Park discloses a publication from a similar field of endeavor in which: at least one of the first portion and the second portion comprises a light-transmitting bank pattern (120) and a light-shielding bank pattern (110); the light-transmitting bank pattern is provided with a groove (120g) arranged in a direction in which the at least one of the first portion and the second portion extends, the light- shielding bank pattern is filled in the groove; the color conversion pattern (320) is arranged in the first opening, and a first step (step shown between 120 and 320) is between the color conversion pattern and the separation bank in a direction perpendicular to the base substrate, and the leveling layer (500) at least partially fills the first opening to fill the first step (Fig. 5). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the configuration of the bank region of Park within the similar structure of Kim such that the leveling layer forms a flat surface at a side away from the base substrate to determine a sufficiently high height light-shielding member thereby further increasing suppression of light leakage defect between adjacent pixels (see Park para 0111-0112). Regarding claims 17-20, Kim discloses: A method for manufacturing a display substrate (Figs. 3-8 and 11), the method comprising: forming a light-emitting substrate (Fig. 11), wherein the light-emitting substrate comprises a base substrate (SUB), a plurality of light-emitting devices (DPL), a plurality of switch elements (PCL) and an encapsulation layer (INS4) which are arranged on the base substrate, wherein the switch element is configured to drive the light-emitting device to emit light, the encapsulation layer encapsulates the light-emitting device, and at least one light-emitting device and at least one switch element are arranged in each pixel correspondingly (Figs. 3-8); forming a color conversion layer (CCL) at a side of the encapsulation layer away from the base substrate, wherein the color conversion layer comprises a separation bank (BNK2), a color conversion pattern (CCL) and a leveling layer (LRL); the separation bank comprises a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction, the first direction intersects with the second direction and is parallel to the base substrate; the plurality of first portions and the plurality of second portions intersect with each other to define a plurality of first openings corresponding to the plurality of pixels (para 0162; BNK2 surrounding light emitting areas and pixels) (Fig. 11); and forming a color filtering layer (CFL) at a side of the color conversion layer away from the base substrate, wherein the color filtering layer comprises a light-shielding pattern (BM) and a color filtering pattern (CF1, CF2, CF3), the light-shielding pattern defines second openings corresponding to the plurality of first openings, and the color filtering pattern is arranged in the second opening (Fig. 11). Kim does not disclose: the separation bank is divided into a light-transmitting bank pattern and a light-shielding bank pattern; the light-transmitting bank pattern is provided with a groove arranged along at least one of a first direction and the second direction; the light-shielding bank pattern is filled in the groove; the color conversion pattern is arranged in the first opening, and a first step is between the color conversion pattern and the separation bank in a direction perpendicular to the base substrate, and the leveling layer at least partially fills the first step and form a flat surface at a side away from the base substrate. Park discloses a publication from a similar field of endeavor in which: the separation bank is divided into a light-transmitting bank pattern (120) and a light-shielding bank pattern (110); the light-transmitting bank pattern is provided with a groove (120g) arranged along at least one of a first direction and the second direction, the light-shielding bank pattern is filled in the groove; the color conversion pattern (320) is arranged in the first opening, and a first step (step shown between 120 and 320) is between the color conversion pattern and the separation bank in a direction perpendicular to the base substrate, and the leveling layer (500) at least partially fills the first step (Fig. 5). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the configuration of the bank region of Park within the similar structure of Kim such that the leveling layer forms a flat surface at a side away from the base substrate to determine a sufficiently high height light-shielding member thereby further increasing suppression of light leakage defect between adjacent pixels (see Park para 0111-0112). (claims 18-20) Park: Fig. 5; light-transmitting layer, groove and first opening, light-shielding layer, color conversion layer (para 0098-0120); Kim: leveling layer (para 0186). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Dec 21, 2023
Application Filed
Sep 03, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745469
SOLID-STATE IMAGING ELEMENT AND IMAGING SYSTEM
4y 1m to grant Granted Sep 22, 2026
Patent 12740098
TRANSISTORS WITH MITIGATED FREE BODY EFFECT
3y 0m to grant Granted Sep 15, 2026
Patent 12740124
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
3y 0m to grant Granted Sep 15, 2026
Patent 12727494
SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER
3y 9m to grant Granted Sep 01, 2026
Patent 12727460
INTEGRATED CIRCUIT STRUCTURE WITH RECESSED TRENCH CONTACT AND DEEP BOUNDARY VIA
3y 9m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.8%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month