DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of claim 2, reciting: “method of forming a drain conductive layer on the bottom surface of the substrate,” and in claims 8, 15, reciting: “a source passivation layer,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2,3,12,13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, it is not clear how the method of forming a drain conductive layer on the bottom surface of the substrate is effectuated. That is, the drain represented by (5) is formed on the bottom surface of 12. In contrast, claim 1 depict the substrate as the drift region (2) that is clearly not abutted to the drain conductive layer (5). Therefore, the limitation above does not make sense. Additionally, the limitation: “the buffer layer being located between the drift region and the emitter is not clear. An emitter is typically not formed below a buffer layer and below the trenches (see super junction devices in US 2007/0114598, US2021/0098569, US2022/0416063, and US2021/0384190. Simply put, item 12 should depict a collector, according to the IGBT technology, rather than an emitter.
Claim 3 depends on claim 2 and will inherit the deficiencies of claim 2. Thus, it is also rejected under 112.
Regarded claim 12, the limitation: “the buffer layer is located on a back side of the drift region, the emitter is located on a back side of the buffer layer” is not clear. As explained above, an emitter is typically not formed below a buffer layer and below the trenches (see super junction devices in US 2007/0114598, US2021/0098569, US2022/0416063, and US2021/0384190. Simply put, item 12 should depict a collector, according to the IGBT technology, rather than an emitter.
Claim 13 depends on claim 12 and will inherit the deficiencies of claim 2. Thus, it is also rejected under 112.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,4,6,7,9-11,14 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Fukui et al., (Fukui) US 2021/0288156.
Regarding claim 1, Fukui shows in FIG.3, (fig. 3, 5-15, par. 83-100) a method for
manufacturing an insulated gate bipolar transistor with a super junction structure, comprising: providing a first conductive type substrate (3) to form a first conductive type
drift region (3) (fig. 5, par. 83), and forming a first conductive type epitaxial layer (14) on an upper surface of the substrate (fig. 5, par 83, 84, where reference is made to
layers ref. 14, 4, 5. Note that these layers are formed in a continuous epitaxial
process with layer ref. 3), a doping concentration of the epitaxial layer being higher than a doping concentration of the substrate (par. 83-86. Where reference is made to highly doped layer ref.14); forming a plurality of trenches spaced in the epitaxial layer (fig. 8, ref. 6, par. 89), and forming a second conductive type filling layer (13) in a trench (fig. 3, 9-15, par. 90), an upper surface of the filling layer (13) being lower than a top surface of the epitaxial layer (fig. 3, 9-15); forming a gate dielectric layer (7) on an inner wall of the trench and the upper surface of the filling layer (fig. 3, 13-15, par. 97-98), and forming a gate conductive layer (8) in the trench with, a side wall and a bottom surface of the gate conductive layer (8) being wrapped by the gate dielectric layer (7), an upper surface of the gate conductive layer (8) being lower than the top surface of the epitaxial layer (14) (fig. 3, 13-15, par. 98-100); forming a second conductive type body region (4) in an upper surface layer of the epitaxial layer (14) on both sides of the trench (fig. 3, 8-15, par. 84-87), forming a second conductive type body contact region (4) and a first conductive type source region (5) adjacent to each other in an upper surface layer of the body region (fig. 3, 7-15, par. 85-88), and forming an isolation dielectric layer (9) covering the upper surface of the epitaxial layer (14) and the upper surface of the gate conductive layer (8) (fig. 12, par. 101); and forming a contact hole (where 16 is formed) passing through the isolation dielectric layer (9) to simultaneously expose the source region and the body contact region (fig. 13, par. 101), and forming a source conductive layer (10) filling the contact hole and covering the isolation dielectric layer (fig. 3, par. 104).
Regarding claim 4, Fukui shows in FIG.3, 5-15, a method for manufacturing the insulated gate bipolar transistor with the super junction structure, wherein the first conductive type is opposite to the second conductive type, the first conductive type comprises one of an N-type and a P-type, and the second conductive type comprises the other of the N-type and the P-type [0066].
Regarding claim 6, Fukui shows in FIG.3, 5-15, a method for manufacturing the insulated gate bipolar transistor with the super junction structure, wherein the forming the gate conductive layer (8) comprises: forming a gate conductive material (8) (see FIG. 11,12) in the trench and on the epitaxial layer (14); removing the gate conductive material (FIG. 11,12 shows portion of 8 removed) on the epitaxial layer, and removing the gate conductive material in the trench to a preset depth to form the gate conductive layer (final gate 8 formed in FIG. 12).
Regarding claim 7, Fukui shows in FIG.3, 5-15, a method for manufacturing the insulated gate bipolar transistor with the super junction structure, wherein the upper surface of the filling layer (13) and a lower surface of the gate conductive layer (8) are lower than a bottom surface of the body region (4).
Regarding claim 9, Fukui shows in FIG.3, 5-15, a method for manufacturing the insulated gate bipolar transistor with the super junction structure, wherein the doping concentration of the epitaxial layer (14) is higher than a doping concentration of the drift region [0083, 0086].
Regarding claim 10, Fukui shows in FIG.3, 5-15, par. 83-104 discloses an insulated gate bipolar transistor with a super junction structure comprising: a drift region (fig. 3, 5-15, ref. 3, par. 83); an epitaxial layer located on an upper surface of the drift region (fig. 5, par 83, where reference is made to layers ref. 14, 4, 5. Noting also, that "epitaxial layer" does not further specify a "layer" within the context of a device claim, as the manufacturing method is indiscernible in a device after manufacturing), a doping concentration of the epitaxial layer being higher than a doping concentration of the substrate (par. 83. Where reference is made to layer ref. 14); a plurality of trenches spaced which are located in the epitaxial layer (fig. 8, ref. 6, par. 89); a second conductive type filling layer (13) (fig. 3, 9-15, par. 90) and a gate structure sequentially arranged in the trench from bottom to top, wherein the gate structure comprises a gate dielectric layer (7) and a gate conductive layer (8)(fig. 3, 13-15, par. 98-100), and the gate dielectric layer (7) is located on an inner wall of a trench and an upper surface of the filling layer (13) and wraps a side wall and a bottom surface of the gate conductive layer (8) (fig. 3, 13-15, par. 97-98) a second conductive type body region located in an upper surface layer of the epitaxial layer on both sides of the trench (fig. 3, 8-15, ref. 4 par. 84-87) a second conductive type body contact region (4) and a first conductive type source region (5) adjacent to each other located in an upper surface layer of the body region(4) (fig. 3, 7-15, ref. 5, 15, par. 85-88); an isolation dielectric layer (9) covering an upper surface of the source region (5) and an upper surface of the gate conductive layer (8) (fig. 3, 13-15, par. 101), wherein a contact hole (area where 16 is formed) passing through the isolation dielectric layer (9) is provided in the isolation dielectric layer, and the contact hole simultaneously exposes the source region (5) and the body contact region (4) (fig. 13, par. 101); and a source conductive layer (10) filling the contact hole and covering the isolation dielectric layer (9) (fig. 3, par. 104).
14. The insulated gate bipolar transistor with the super junction structure according to claim 10, wherein the first conductive type is opposite to the second conductive type, the first conductive type comprises one of an N-type and a P-type, and the second conductive type comprises the other of the N-type and the P-type.
Regarding claim 11, Fukui shows in FIG.3, 5-15, an insulated gate bipolar transistor with the super junction structure, wherein the upper surface of the filling layer (13) and a lower surface of the gate conductive layer (8) are lower than a bottom surface of the body region (4).
Regarding claim 14, Fukui shows in FIG.3, 5-15, an insulated gate bipolar transistor with the super junction structure, wherein the first conductive type is opposite to the second conductive type, the first conductive type comprises one of an N-type and a P-type, and the second conductive type comprises the other of the N-type and the P-type [0066].
Claim(s) 5 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Fukui as applied to claims 1,4,6,7,9-11,14, and further in view of Yilmaz US 2019/0348510.
Regarding claim 5, Fukui discloses a method for manufacturing the insulated gate bipolar transistor with the super junction structure, wherein the forming the filling layer comprises: forming a second conductive type conductive material (13) in the trench and on the upper surface of the epitaxial layer.
Fukui differs from the claimed invention because he does not explicitly disclose a device removing the conductive material on the upper surface of the epitaxial layer, and removing the conductive material in the trench to a preset depth to form a second conductive type filling layer.
Yilmaz shows in FIG. 5F-5T, a device removing the conductive material (18) on the upper surface of the epitaxial layer, and removing the conductive material (18 is removed) in the trench to a preset depth to form a second conductive type filling layer.
Yilmaz is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Fukui. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yilmaz in the device of Fukui because it will improve the reliability of the device [0019].
Claim(s) 8,15 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Fukui as applied to claims 1,4,6,7,9-11,14, and further in view of Nakamura US 2022/0262638.
Regarding claims 8,15, Fukui discloses a method for manufacturing the insulated gate bipolar transistor with the super junction structure.
Fukui differs from the claimed invention because he does not explicitly disclose a method of forming a source passivation layer on an upper surface of the source conductive layer.
Nakamura shows in FIG. 28, a method of forming a source passivation layer (30) on an upper surface of the source conductive layer.
Nakamura is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Fukui. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Nakamura in the device of Fukui because it will protect the device [0105].
Claim(s) 12,13 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Fukui as applied to claims 1,4,6,7,9-11,14, and further in view of Yamashita et al., (Yamashita) US 2014/0048847.
Regarding claims 12,13, Fukui discloses a method for manufacturing the insulated gate bipolar transistor with the super junction structure.
Fukui differs from the claimed invention because he does not explicitly disclose a device comprising a first conductive type buffer layer, a second conductive type emitter and a drain conductive layer, wherein the buffer layer is located on a back side of the drift region, the emitter is located on a back side of the buffer layer, the drain conductive layer is located on a back side of the emitter; wherein a doping concentration of the buffer layer is higher than a doping concentration of the drift region.
Yamashita shows in FIG. 7, a device comprising a first conductive type buffer layer (8), a second conductive type emitter (6 can be used as the emitter) and a drain conductive layer (20), wherein the buffer layer (8) is located on a back side of the drift region (10), the emitter (6) is located on a back side of the buffer layer (8), the drain conductive layer (20) is located on a back side of the emitter (6); wherein a doping concentration of the buffer layer (8) is higher than a doping concentration of the drift region (10, n- layer).
Yamashita is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Fukui. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yamashita in the device of Fukui because it will provide a device that can reduce loss at the time of switching in a diode [0004].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARC - ANTHONY ARMAND
Examiner
Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813