Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-35 are rejected under 35 U.S.C. 102(a)92) as being anticipated by Choi (20150014630).
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Regarding claim 16, Choi teaches a Negative differential resistance tunnel diode (please see tunneling device above; please note that tunnel diodes exhibit negative differential resistance due to quantum tunneling, allowing them to decrease current flow as voltage increases) comprising two terminals for connecting to an electrical circuit (please see E1 and E2 which allow for the flow of current into tunneling device) as well as a tunnel junction (par. 66 teaches a tunnel junction) having a first material layer (fig. 1: ML1) of a cold metal (par. 57 and 62; please note that cold metals are materials with narrow metallic bands near the Fermi level, often exhibiting low electronic thermal excitations; these materials include but are not limited to 2D materials), an insulating material layer (fig. 1: TL1; par. 57 and 62) of a tunnel barrier, and a second material layer of a cold metal (par. 57 and 62; please note that cold metals are materials with narrow metallic bands near the Fermi level, often exhibiting low electronic thermal excitations; these materials include but are not limited to 2D materials).
Regarding claim 17, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the first material layer and the second material layer are of the same cold metal material (par. 57 and 62).
Regarding claim 18, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein at least one dielectric layer (par. 58 teaches SiO2 on the subtrate) is provided adjacent to the tunnel junction for depositing the first material layer, the insulating material layer of a tunnel barrier, and/or the second material layer.
Regarding claim 19, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the cold metal can be identified by having in a density of states representation (DOS) of electrons of the cold metal: a conduction band width CBW starting at a Fermi Energy EF level towards higher energy E, a valence band width VBW starting at the Fermi Energy EF level towardslower energy E, a conduction band gap CBG adjacent to the conduction band width CBW towards higher energy E, and a valence band gap VBG adjacent to the valence band width VBW towards lower energy E (par. 57 and 62 teaches these types of materials).
Regarding claim 20, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the cold metal is a material with spin-polarized ground state or a paramagnetic cold metal (par. 57 and 62 teaches these types of materials).
Regarding claim 21, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the cold metal is TaX2, wherein X is one of S, Se and Te (par. 57 and 62 teaches these types of materials).
Regarding claim 22, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the tunnel junction is a planar tunnel junction, wherein the first material layer, the insulating material layer of the tunnel barrier and the second material layer are arranged on a same plane (as seen in fig. 1, the plane going from the top to bottom of the page goes through layers ML1, TL1 and ML2).
Regarding claim 23, Choi teaches a Negative differential resistance tunnel diode of claim 18, wherein the first material layer, the insulating material layer of the tunnel barrier and the second material layer are deposited on a surface of the at least one dielectric layer, which is adjacent to the planar tunnel junction (please see fig. 1 and rejection for claim 18 above).
Regarding claim 24, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the tunnel junction is a vertical tunnel junction (par. 66), wherein the first material layer, the insulating material layer of the tunnel barrier and the second material layer are arranged in a stacked manner.
Regarding claim 25, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the first material layer is protruding the insulating material layer of the tunnel barrier in a horizontal direction for connecting to the first terminal (please see the configuration seen in fig. 1).
Regarding claim 26, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the second material layer is protruding the insulating material layer of the tunnel barrier in an opposite horizontal direction for connecting to the second terminal (please see the configuration seen in fig. 1).
Regarding claim 27, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the first material layer and the insulating material layer of the tunnel barrier are twisted with an offset angle relatively to each other (please see the configuration seen in fig. 1).
Regarding claim 28, Choi teaches a Negative differential resistance tunnel diode of claim 27, wherein the offset angle measures a rotation of a layer in the plane of the layer, i.e. about an axis that is oriented orthogonal to the layers (please see the configuration seen in fig. 1 above).
Regarding claim 29, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the insulating material layer of the tunnel barrier and the second material layer are twisted with an offset angle relatively to each other (please see the configuration seen in fig.1 above).
Regarding claim 30, Choi teaches a Negative differential resistance tunnel diode of claim 29, wherein the offset angle measures a rotation of a layer in the plane of the layer, i.e. about an axis that is oriented orthogonal to the layers (please see the configuration seen in fig. 1 above).
Regarding claim 31, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein at least two of the first material layer , the insulating material layer of the tunnel barrier and the second material layer are twisted with an offset angle relatively to each other (please see the configuration seen in fig. 1).
Regarding claim 32, Choi teaches a Negative differential resistance tunnel diode of claim 18, wherein the at least one dielectric layer fills a horizontal space between one of the terminals and the tunnel barrier (the SiO2 mentioned in par. 57 is between the substrate and the layers/elelctrodes seen in fig. 1).
Regarding claim 33, Choi teaches a Negative differential resistance tunnel diode of claim 16, wherein the tunnel junction is arranged between both terminals in a direction of long axes of the first and second material layer, which are extending in parallel to each other (please see par. 57, 62 and 66).
Regarding claim 34, Choi teaches a Use of the negative differential resistance tunnel diode of claim 16 for one of memory applications and logic applications (par. 6).
Further, claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 35, Choi teaches a Method for manufacturing a negative differential resistance tunnel diode, comprising the steps of:
Depositing a first material layer of a cold metal, an insulating material layer of a tunnel barrier and a second material layer of a cold metal (par. 26-34 and 54-64);
Depositing a first terminal to the first material layer and the second terminal to the second material layer (par. 26-34 and 54-64).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
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/CALEB E HENRY/Primary Examiner, Art Unit 2818
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