Prosecution Insights
Last updated: April 19, 2026
Application No. 18/573,297

POWER MODULE

Non-Final OA §102§103
Filed
Dec 21, 2023
Examiner
OWENS, DOUGLAS W
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Amosense Co. Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
84%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
265 granted / 328 resolved
+12.8% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
357
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 328 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication US 2014/0110833 to Yoo et al. Regarding claim 1, Yoo et al. teach a power module comprising: a base plate (111); a ceramic substrate (113; ¶ [0029]) bonded to an upper surface of the base plate; a semiconductor chip (120a) bonded to an upper surface of the ceramic substrate; a spacer (115b) bonded to the upper surface of the ceramic substrate to be spaced apart from the semiconductor chip; a connecting pin (130a; ¶ [0014]) installed on an electrode layer formed on an upper surface of the spacer; and a bonding wire (121) connecting terminals of the semiconductor chip to the electrode layer of the spacer. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. Regarding claim 2, Yoo et al. teach a power module, further comprising a printed circuit board (PCB) substrate connected to the connecting pin, wherein the semiconductor chip is electrically connected to the PCB substrate through the bonding wire, the electrode layer, and the connecting pin. Yoo et al. do not explicitly teach that the PCB is disposed above the ceramic substrate. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to dispose the PCB above the ceramic substrate since it is desirable to provide a base for the PCB, as well as not needing to add the additional step of creating a via through the substrate to provide connection to the pin. Regarding claim 5, Yoo et al. do not teach a power module wherein the semiconductor chip is a gallium nitride (GaN) chip. GaN is a well-known material that is ideally suited for use in power modules. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use a GaN chip, since it is a known material that is well suited for the intended use. Regarding claim 6, Yoo et al. do not teach a power module wherein the ceramic substrate is an active metal brazing (AMB) substrate. Yoo et al. do not teach or suggest any specific type of ceramic. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to select an active metal brazing substrate since this is a known material that is well suited for the intended use. Allowable Subject Matter Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 7 – 16 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or reasonably suggest a power module as recited in claims 7 and 11, including “an upper ceramic substrate disposed to be spaced apart above the lower ceramic substrate” (claim 7), and “a printed circuit board (PCB) substrate disposed above the ceramic substrate and including a driving device; and a lead wire connecting a terminal of the semiconductor chip to the driving device.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2023/0238315 to Qiao et al., an intervening reference, teach a power module including a ceramic substrate, a spacer, a connecting pin on an upper surface of the space. Qiao et al. do not teach the bonding wire connected to the spacer electrode and terminals of a semiconductor chip. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DOUGLAS W. OWENS, Esq. Primary Patent Examiner Art Unit 2897 /DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Dec 21, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12593716
SUBSTRATE ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12588538
SEMICONDUCTOR DEVICE HAVING WIRED UNDER BUMP STRUCTURE AND METHOD THEREFOR
2y 5m to grant Granted Mar 24, 2026
Patent 12581937
INTEGRATED DEVICE COMPRISING METALLIZATION INTERCONNECTS
2y 5m to grant Granted Mar 17, 2026
Patent 12564085
MICROELECTRONIC ASSEMBLY WITH UNDERFILL FLOW CONTROL
2y 5m to grant Granted Feb 24, 2026
Patent 12563882
ELECTRONIC DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
84%
With Interview (+2.8%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 328 resolved cases by this examiner. Grant probability derived from career allow rate.

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