DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Preliminary Amendment
Applicant’s 12/22/2023 Preliminary Amendment to: 1. Amend the instant Specification is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: HIGH-MOBILITY SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND WIRELESS COMMUNICATION APPARATUS.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 7-9 and 11-14 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 6-13 of copending Application No. 19/100,311. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1 and 6-13 of copending Application No. 19/100,311 anticipate claims 1, 7-9 and 11-14 of the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
A. Regarding instant claim 1, copending Application No. 19/100,311 claims 1 and 9 disclose:
a semiconductor device, comprising:
a channel layer including a first nitride semiconductor, the first nitride semiconductor having a first band gap (as recited in lines 1-5 of claim 1);
a barrier layer including a second nitride semiconductor, the second nitride semiconductor having a second band gap larger than the first band gap of the first nitride semiconductor (as recited in lines 6-11 of claim 1);
a first spacer layer provided between the channel layer and the barrier layer, the first spacer layer including Alx1Iny1Ga(1-x1-y1)N (0 < x1 ≤ 1, 0 ≤ y1 < 1, 0 ≤ x1 + y1 ≤ 1; as recited in lines 1-5 of claim 9); and
a second spacer layer provided between the first spacer layer and the barrier layer, the second layer including Alx2Iny2Ga(1-x2-y2)N (0 < x2 < x1 ≤ 1, 0 ≤ y2 < 1, 0 ≤ x2 + y2 < 1; as recited in lines 5-7 of claim 9).
B. Regarding instant claim 7, copending Application No. 19/100,311 claim 6 discloses:
wherein the x3 is over 0.7, and the y3 is below 0.3 (as recited in lines 1-2).
C. Regarding instant claim 8, copending Application No. 19/100,311 claim 7 discloses:
wherein the barrier layer has a thickness of 2.0 nm or more and 20 nm or less (as recited lines 2-3).
D. Regarding instant claim 9, copending Application No. 19/100,311 claim 8 discloses:
further comprising a protection layer on an opposite side of the second spacer layer with the barrier layer in between, the protection layer including Alx4Iny4Ga(1x4-y4)N (0 ≤ x4 < 1, 0 ≤ y4 < 1) and satisfying (1-x3-y3) < (1-x4-y4 as recited in lines 1-5).
E. Regarding instant claim 11, copending Application No. 19/100,311 claim 10 discloses:
wherein the channel layer includes at least one type from among GaN (gallium nitride), InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride), and AllnGaN (aluminum indium gallium nitride as recited lines 2-5).
F. Regarding instant claim 12, copending Application No. 19/100,311 claim 11 discloses:
wherein the substrate includes at least one type from among Si (silicon), sapphire, SiC (silicon carbide), GaN (gallium nitride), and AIN (aluminum nitride as recited lines 2-4).
G. Regarding instant claim 13, copending Application No. 19/100,311 claim 12 discloses:
an insulating film (as recited line 3);
a gate electrode (as recited in line 4);
a source electrode (as recited in line 5); and
a drain electrode (as recited in line 6),
the insulating film, the gate electrode, the source electrode, and the drain electrode being provided on an opposite side of the second spacer layer with the barrier layer (as recited in lines 7-10).
H. Regarding instant claim 14, copending Application No. 19/100,311 claim 13 discloses:
an insulating film (as recited in line 3);
a gate electrode (as recited in line 4);
a source electrode (as recited in line 5); and
a drain electrode (as recited in line 6),
the insulating film, the gate electrode, the source electrode, and the drain electrode being provided on the protection layer (as recited in lines 7-9).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 12 is rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim 12 recites the limitation "wherein the substrate" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 1, "wherein the substrate" in lines 1-2 will be interpreted to read as "wherein the channel layer is on a substrate, the substrate".
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12; and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Saxler (US 2003/0102482 A1) in view of KOTANI et al (US 2016/0359032 A1, hereafter Kotani).
Re claim 1, Saxler discloses in FIG. 4 (with references to FIG. 1) a semiconductor device (HEMT; [0002]), comprising:
a channel layer (18; [0034] and [0042]) including a first nitride semiconductor (GaN; [0042]), the first nitride semiconductor (GaN) having a first band gap (~3.4 eV);
a barrier layer including (20’; [0042]) a second nitride semiconductor (AlN; [0042]), the second nitride semiconductor (AlN) having a second band gap (~6 eV) larger than (exceeding) the first band gap (~3.4 eV) of the first nitride semiconductor (GaN).
Saxler fails to disclose a first spacer layer provided between the channel layer and the barrier layer, the first spacer layer including Alx1Iny1Ga(1-x1-y1)N (0 < x1 ≤ 1, 0 ≤ y1 < 1, 0 ≤ x1 + y1 ≤ 1); and a second spacer layer provided between the first spacer layer and the barrier layer, the second layer including Alx2Iny2Ga(1-x2-y2)N (0 < x2 < x1 ≤ 1, 0 ≤ y2 < 1, 0 ≤ x2 + y2 < 1).
However,
Kotani discloses in FIG. 8B (with references to FIG. 1A) a semiconductor device, comprising: a first spacer layer (32; [0075]) provided on a channel layer (2b; [0032] and [0072]), the first spacer layer (32) including InxAlyGa(1-x-y)N, and a composition ratio of In is 0.2 or less (0<x≦0.2), and a composition ratio of Al is not less than 0.2 nor more than 0.7 (0.2≦y≦0.7); and
a second spacer layer (33; [0075]) provided on the first spacer layer (32), the second layer including AlxGa1-xN, and a composition ratio of Al is not less than 0.2 nor more than 0.7 (0.2≦x≦0.7).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Saxler by adding the first and second spacer layers of Kotani, the first spacer layer including Alx1Iny1Ga(1-x1-y1)N (0 < x1 ≤ 1, 0 ≤ y1 < 1, 0 ≤ x1 + y1 ≤ 1); and a second spacer layer provided between the first spacer layer and the barrier layer, the second layer including Alx2Iny2Ga(1-x2-y2)N (0 < x2 < x1 ≤ 1, 0 ≤ y2 < 1, 0 ≤ x2 + y2 < 1), through routine experimentation (MPEP § 2144.05), to obtain high surface smoothness, and minimum stress in the interface with the channel. Thereby, the electron (2DEG) mobility of the channel improves (Kotani; [0080]).
Re Claim 2, Saxler discloses the semiconductor device according to claim 1, wherein the second nitride semiconductor (AlN) includes Alx3Iny3Ga(1x3-y3)N (0 < x2 < x3 < 1, 0 ≤ y3 < 1, when y3=0).
Re Claims 3-4, Saxler and Kotani disclose the semiconductor device according to claim 1, wherein the first spacer layer (Kotani: 32) has a thickness of 0.26 nm or more (1 nm; [0074]) and 3.0 nm or less (1 nm; [0074]); and wherein the second spacer layer (Kotani: 33) has a thickness of 0.26 nm or more (1 nm; [0074]) and 3.0 nm or less (1 nm; [0074]), as would be part of the channel interfaces discussed for claim 1.
Re Claim 5, Saxler and Kotani disclose the semiconductor device according to claim 1.
But, fails to disclose wherein the y1 is 0.
However, Kotani discloses in the embodiment of FIG. 9B wherein the y1 is 0 ([0085]) of first spacer layer (42; [0085]), in order to to internally contain tensile crystal distortion due to a difference in lattice constant from the GaN channel. Thereby, there is fabricated a high-quality spacer structure in which the crystal distortion is cancelled out. Accordingly, the first and second spacer layers internally contains no crystal distortion and the electron (2DEG) mobility of the channel improves (Kotani; [0090]).
Re Claim 6, Saxler and Kotani disclose the semiconductor device according to claim 1, wherein the y2 is 0 (for AlxGa1-xN 33 of Kotani), as would be part of the channel interfaces discussed for claim 1.
Re Claim 7, Saxler discloses the semiconductor device according to claim 2.
But, fails to explicitly disclose wherein the x3 is over 0.7, and the y3 is below 0.3.
However, Saxler discloses x3 can be between 0.05-1.0 ([0041]), which would yield y3 below 0.3 when x3 > 0.7 for AlGaN barrier (20’), to increase or maximize carrier concentration in the channel layer (Saxler; [0009]).
Re Claim 8, Saxler discloses the semiconductor device according to claim 1, wherein the barrier layer (20’) has a thickness of 2.0 nm or more (at least 10 nm; [0041]) and 20 nm or less (at least 10 nm; [0041]).
Re Claim 9, Saxler and Kotani disclose the semiconductor device according to claim 1, further comprising a protection layer (22; [0042]) on an opposite side (upper plane) of the second spacer layer (Kotani: 33) with the barrier layer (Saxler: 20’) in between, the protection layer (22) including Alx4Iny4Ga(1x4-y4)N (0 ≤ x4 < 1, 0 ≤ y4 < 1; AlGaN, when 0 ≤ x ≤ 1, y=0; [0042]) and satisfying (1-x3-y3, when x3=0.05-1.0; [0041]) < (1-x4-y4, when 0 ≤ x ≤ 1, y=0; [0042]), as would be part of the structure to increase or maximize carrier concentration in the channel layer (Saxler; [0009]) discussed for claim 7.
Re Claim 10, Saxler discloses the semiconductor device according to claim 1, wherein the first nitride semiconductor (GaN) includes Alx5Iny5Ga(1x5-y5)N (0 ≤ x5 ≤ 1, 0 ≤ x5 + y5 ≤ 1, when x5=y5=0).
Re Claim 11, Saxler discloses the semiconductor device according to claim 1, wherein the channel layer (18) includes at least one type from among GaN (gallium nitride; [0042]), InGaN (indium gallium nitride), InN (indium nitride), AlGaN (aluminum gallium nitride), and AllnGaN (aluminum indium gallium nitride).
Re Claim 12, Saxler discloses the semiconductor device according to claim 1, wherein the channel layer (18) is on a substrate (12; [0018] and [0029]), the substrate (12) includes at least one type from among Si (silicon; [0018]), sapphire ([0018]), SiC (silicon carbide; [0018] and [0029]), GaN (gallium nitride), and AIN (aluminum nitride; [0018]).
Re claim 16, Saxler discloses in FIG. 4 (with references to FIG. 1) a semiconductor module (unspecified assembly for a high frequency application; [0003]) comprising a semiconductor device (HEMT; [0002]), the semiconductor device (HEMT) including:
a channel layer including a first nitride semiconductor, the first nitride semiconductor having a first band gap (see claim 1);
a barrier layer including a second nitride semiconductor, the second nitride semiconductor having a second band gap larger than the first band gap of the first nitride semiconductor (see claim 1).
Saxler fails to disclose a first spacer layer provided between the channel layer and the barrier layer, the first spacer layer including Alx1Iny1Ga(1-x1-y1)N (0 < x1 ≤ 1, 0 ≤ y1 < 1, 0 ≤ x1 + y1 ≤ 1); and a second spacer layer provided between the first spacer layer and the barrier layer, the second layer including Alx2Iny2Ga(1-x2-y2)N (0 < x2 < x1 ≤ 1, 0 ≤ y2 < 1, 0 ≤ x2 + y2 < 1).
However, Kotani renders these limitations obvious (see claim 1) for a semiconductor module (high frequency amplifier; [0120] and [0122]) to obtain high surface smoothness, and minimum stress in the interface with the channel. Thereby, the electron (2DEG) mobility of the channel improves (Kotani; [0080]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Saxler (US 2003/0102482 A1) in view of KOTANI et al (US 2016/0359032 A1, hereafter Kotani) and Jones et al (US 2021/0217883 A1, hereafter).
Re Claim 17, Saxler discloses in FIG. 4 (with references to FIG. 1) a semiconductor, the semiconductor device including:
a channel layer including a first nitride semiconductor, the first nitride semiconductor having a first band gap (see claim 1);
a barrier layer including a second nitride semiconductor, the second nitride semiconductor having a second band gap larger than the first band gap of the first nitride semiconductor (see claim 1).
A. Saxler fails to disclose a first spacer layer provided between the channel layer and the barrier layer, the first spacer layer including Alx1Iny1Ga(1-x1-y1)N (0 < x1 ≤ 1, 0 ≤ y1 < 1, 0 ≤ x1 + y1 ≤ 1); and a second spacer layer provided between the first spacer layer and the barrier layer, the second layer including Alx2Iny2Ga(1-x2-y2)N (0 < x2 < x1 ≤ 1, 0 ≤ y2 < 1, 0 ≤ x2 + y2 < 1).
However, Kotani renders these limitations obvious (see claim 1) for a semiconductor module (high frequency amplifier; [0120] and [0122]) to obtain high surface smoothness, and minimum stress in the interface with the channel. Thereby, the electron (2DEG) mobility of the channel improves (Kotani; [0080]).
B. Saxler and Kotani fail to disclose a wireless communication apparatus comprising the semiconductor device (HEMT).
However,
Jones discloses in FIG. 3 a wireless communication apparatus (for telecommunications; [0005] and [0038]) comprising a semiconductor device (HEMT 10/capacitor 18; [0047]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Saxler and Kotani by combining the capacitor of Jones with the HEMT of Saxler and Kotani, reducing the area required for high power and high temperature device operation at high frequencies (Jones; [0005] and [0010]).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Saxler and Kotani as applied to claim 1 above, and further in view of Yanagihara et al (US 2005/0263791 A1, hereafter Yanagihara).
Re Claim 13-14, Saxler and Kotani disclose the semiconductor device according to claim 1, further comprising: a gate electrode (36; [0043]); a source electrode (35; [0043]); and a drain electrode (37; [0043]), the gate electrode (36), the source electrode (35), and the drain electrode (37) being provided on an opposite side (upper plane) of the barrier layer (20’); and further comprising: a gate electrode (36); a source electrode (35); and a drain electrode (37), the gate electrode (36), the source electrode (35), and the drain electrode (37) being provided on the protection layer (22).
Saxler and Kotani fail to disclose an insulating film, the insulating film, the gate electrode (36), the source electrode (35), and the drain electrode (37) being provided on an opposite side of the second spacer layer (Kotani: 33) with the barrier layer (20’) in between; and an insulating film, the insulating film being provided on the protection layer (22).
However,
Yanagihara discloses in FIG. 1 a semiconductor device comprising an insulating film (7; [0119] and [0127]), the insulating film (7), a gate electrode (6; [0119] and [0127]), the source electrode (4; [0119] and [0127]), and the drain electrode (5; [0119] and [0127]) being provided on a spacer layer (12; [0103]) and a barrier layer (13; [0103]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Saxler and Kotani by adding the insulating film of Yanagihara, the insulating film, the gate electrode (36), the source electrode (35), and the drain electrode (37) being provided on an opposite side of the second spacer layer (33) with the barrier layer (20’) in between; and the insulating film, the insulating film being provided on the protection layer (22), to protect the upper surface of the protection layer (22), and prevent shorting of the gate electrode (36), the source electrode (35), and the drain electrode (37).
Re Claim 15, Saxler discloses the semiconductor device according to claim 14.
But, fails to disclose wherein the semiconductor device (HEMT) has a Schottky gate configuration in which the protection layer (22) and the gate electrode (36) are joined by Schottky barrier junction, and an off-state leakage current is below 1e-4 [A/mm].
However, Yanagihara discloses a Ni/Au Schottkey gate electrode (6; [0119]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Saxler and Kotani by using the gate electrode materials of Yanagihara for the gate electrode of Saxler, to produce a Schottky gate configuration in which the protection layer (22) and the gate electrode (36) are joined by Schottky barrier junction, controlling drain current of the semiconductor device (HEMT; Yanagihara; [0103]).
With respect to the limitation of an off-state leakage current is below 1e-4 [A/mm], the structure of Saxler and Kotani and Yanagihara is substantially identical to the claimed structure, using substantial identical materials (Ni/Au gate electrode contacting an AlGaN protection layer as disclosed by the instant specification). Therefore, it would be expected that structure demonstrates the characteristic of an off-state leakage current below 1e-4 [A/mm]. Thus, producing a prima facie case of obviousness (MPEP § 2112.01).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC W JONES/Primary Examiner, Art Unit 2892