Prosecution Insights
Last updated: July 17, 2026
Application No. 18/573,490

SILICON CARBIDE EPITAXIAL SUBSTRATE, METHOD OF MANUFACTURING SILICON CARBIDE EPITAXIAL SUBSTRATE, AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Dec 22, 2023
Priority
Jul 08, 2021 — JP 2021-113366 +1 more
Examiner
CAMPBELL, SHAUN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Minebea Mitsumi Inc.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
760 granted / 1044 resolved
+4.8% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
28 currently pending
Career history
1086
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
88.3%
+48.3% vs TC avg
§102
7.0%
-33.0% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1044 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Preliminary amendment, received 12/22/2023, has been entered. Claims 1-14 are presented for examination. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asamizu (US Pub. No. 2018/0202070 A1), in view of Wada et al. (US Pub. No. 2018/0363166 A1), hereafter referred to as Wada. As to claim 1, Asamizu discloses a silicon carbide epitaxial substrate (fig 1B, 1; [0089]) comprising: a silicon carbide substrate (fig 1B, substrate 2; [0066]); a silicon carbide epitaxial layer (fig 1B, layer 3; [0089]) located on the silicon carbide substrate (2); and a bump ([0239]) formed on the silicon carbide epitaxial layer (3), wherein the silicon carbide epitaxial layer (3) includes a main surface (top) located opposite to a boundary surface (bottom) between the silicon carbide substrate (2) and the silicon carbide epitaxial layer (3), and a drift layer that constitutes the main surface ([0018]), an area density of the bump is 1.0/cm2 or less on the main surface ([0089]), a polytype of silicon carbide of the bump is the same as a polytype of silicon carbide of the silicon carbide epitaxial layer ([0239]). Asamizu does not disclose the height or diameter of the bump defect, therefore Asamizu does not disclose that the a height of the bump is 50 nm or more, and a diameter of the bump is 5um or more and 30um or less. Nonetheless, Wada discloses wherein a bump defect in a silicon carbide epitaxial substrate is defined with a diameter of more than or equal to 10um ([0116]) and a height of more than several ten nanometer ([0116]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to define the height and diameter of the bump defect of Asamizu within the claimed range as taught by Wada since this will enable the characterization of defects that effect device quality without quantifying defects that are below the defect size threshold. As to claim 2, Asamizu in view of Wada disclose the silicon carbide epitaxial substrate according to claim 1 (paragraphs above). Asamizu further discloses wherein an in-plane uniformity of a carrier concentration in the drift layer is 15% or less ([0088]). As to claim 3, Asamizu in view of Wada disclose the silicon carbide epitaxial substrate according to claim 1 (paragraphs above). Asamizu further discloses wherein an in-plane uniformity of a carrier concentration in the drift layer is 7% or less ([0155]). As to claim 4, Asamizu in view of Wada disclose the silicon carbide epitaxial substrate according to claim 1 (paragraphs above). Asamizu further discloses wherein a diameter of the main surface is 150 mm or more ([0118]). As to claim 5, Asamizu in view of Wada disclose the silicon carbide epitaxial substrate according to claim 1 (paragraphs above). Asamizu further discloses wherein the area density of the bump is 0.5 /cm2 or less ([0089]). As to claim 6, Asamizu in view of Wada disclose the silicon carbide epitaxial substrate according to claim 1 (paragraphs above). Asamizu further discloses wherein an in-plane uniformity of a thickness of the drift layer is 5% or less ([0153]). As to claim 7, Asamizu in view of Wada disclose the silicon carbide epitaxial substrate according to claim 6 (paragraphs above). Asamizu further discloses wherein the in-plane uniformity of the thickness of the drift layer is 3% or less ([0153]). As to claim 8, Asamizu discloses a method of manufacturing a silicon carbide semiconductor device ([0011]), the method comprising: preparing the silicon carbide epitaxial substrate according to claim 1 (paragraphs above); and processing the silicon carbide epitaxial substrate ([0333]-[0334]). Allowable Subject Matter Claims 9-14 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest all of the limitations of independent claim 9. Specifically, neither of the closest prior art references Asamizu or Wada et al. (US Pub. No. 2019/0019868A1) teach or suggest forming a surface-modified layer on the silicon carbide epitaxial layer under a condition of a second C/Si ratio; and removing the surface-modified layer by hydrogen etching, wherein the second C/Si ratio is less than the first C/Si ratio, as recited in claim 9. Dependent claims 10-14 are allowable because of their dependence from claim 9. Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wada et al. (US Pub. No. 2019/0019868A1) teaches forming a first silicon carbide epitaxial layer with a C/Si ratio and a surface modified layer with a lower C/Si ratio but fails to teach wherein the surface modified layer is removed by hydrogen etching. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 4/23/2026
Read full office action

Prosecution Timeline

Dec 22, 2023
Application Filed
May 04, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
81%
With Interview (+8.2%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1044 resolved cases by this examiner. Grant probability derived from career allowance rate.

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