DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 12/26/2023.
Currently claims 1-16 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/11/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4-9 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 4, the instant claim recites limitation in view of claim 1, where claim 4 recites “the first conductive structure is located in the second conductive layer and the second conductive structure is located in the second conductive layer " (claim 4, lines 5-6). It is unclear how both first and second conductive structures are located in the same layer, i.e., ‘second conductive layer’, or the claim meant something else, rendering the claim indefinite. Clarification and/or correction are/is required. Specification para. [0018] – [0029] discuss various possibilities but the one recited in this claim is not one of them. The examiner interpreted it as “the first conductive structure is located in the first conductive layer and the second conductive structure is located in the second conductive layer "
Claims 5-9 are also rejected due to their dependence on a rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 13 and 16 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by CN 113964112 A (Yao).
Regarding claim 1, Yao discloses, a light-emitting baseplate (as annotated on Fig. 1; pages 5-6), comprising a bonding region (A2) and a light-emitting region (A1), wherein the light-emitting baseplate comprises:
a substrate (1; pages 5-6);
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solder pads (2 and 2’; pages 5-6), located on the substrate (1) and in the light-emitting region (A1), wherein the light-emitting region (A1) comprises two layers (5 and 2’) of conductive structure (Fig. 1; pages 5-6);
bonding pins (4), located on the substrate (1) and in the bonding region (A2), wherein the bonding region (A2) comprises one layer (layer of bonding pad 4) of conductive structure (Fig. 1; pages 5-6); and
a first insulation layer (50), located at a side of the bonding pins (4) away from the substrate (1), wherein the first insulation layer (50) is provided with first openings (as annotated on Fig. 1, there will be plurality of openings since the device would have many light-emitting baseplates) located in the bonding region (A2) (Fig. 1; pages 5-6), and
an orthographic projection of each of the first openings (as annotated on Fig. 1) on the substrate (1) is within an orthographic projection of one of the bonding pins (4) on the substrate (1) (Fig. 1; pages 5-6).
Regarding claim 3, Yao discloses, the light-emitting baseplate according to claim 1, wherein the first insulation layer (50) comprises an inorganic layer (silicon nitride, silicon oxide; page 10) located in the bonding region (A2).
Regarding claim 13, Yao discloses, the light-emitting baseplate according to claim 1, wherein the bonding pins (4) comprise a second conductive structure (as annotated on Fig. 1) and second conductive structures of adjacent bonding pins are spaced apart (with multiple light emitting devices, the second conductive structures would obviously be spaced apart).
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Regarding claim 16, Yao discloses, a display apparatus (light emitting system with plurality of light emitting baseplate of Fig. 1; pages 4-5), comprising the light-emitting baseplate according to claim 1 (see the rejection of claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over CN 113964112 A (Yao).
Regarding claim 4, Yao discloses, the light-emitting baseplate according to claim 1, comprising:
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a first conductive layer (layers of bonding pads 2 and 2’) and a second conductive layer (layer of bonding pin 4);
wherein the solder pads (2 and 2’) comprise a first conductive structure (as annotated on Fig. 1) and the bonding pins (4) comprise a second conductive structure (as annotated on Fig. 1); and
the first conductive structure (as annotated on Fig. 1) is located in the interpreted by the examiner) conductive layer (layers of bonding pads 2 and 2’) and the second conductive structure (as annotated on Fig. 1) is located in the second conductive layer (layer of bonding pads 2 and 2’; as evident in Fig. 1; pages 5-6).
But Yao fails to teach explicitly, the second conductive layer located at a side of the first conductive layer away from the substrate;
However, in MPEP 2144.04 (VI) (C), it is stated that Rearrangement of Parts is held to be an obvious matter of design choice, if it does not modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). Therefore, arranging the second conductive layer at a side of the first conductive layer away from the substrate would be obvious. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0020] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Allowable Subject Matter
Claims 2, 5-12 and 14-15 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 2, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 1, further comprising: a flux layer partially located in the first openings, and the flux layer has a thickness greater than a thickness of a part of the first insulation layer in the bonding region”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 1, further comprising: a flux layer partially located in the first openings, and the flux layer has a thickness greater than a thickness of a part of the first insulation layer in the bonding region,’ is material to the inventive concept of the application at hand to use flux layer to bond the bonding pins to the FPC during secondary soldering so as to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Regarding claim 5, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 4, further comprising: a transition region between the bonding region and the light-emitting region, wherein the transition region is provided with a connection trace located in the first conductive layer, and the light-emitting region is provided with a signal trace connected with the connection trace; and the second conductive layer comprises a connection portion located in the transition region, the connection portion is connected with the second conductive structure, and the connection portion is partially located at a side of the connection trace away from the substrate and is connected with the connection trace”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 4, further comprising: a transition region between the bonding region and the light-emitting region, wherein the transition region is provided with a connection trace located in the first conductive layer, and the light-emitting region is provided with a signal trace connected with the connection trace; and the second conductive layer comprises a connection portion located in the transition region, the connection portion is connected with the second conductive structure, and the connection portion is partially located at a side of the connection trace away from the substrate and is connected with the connection trace,’ is material to the inventive concept of the application at hand to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Regarding claim 10, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 1, further comprising: a first conductive layer and a second conductive layer located at a side of the first conductive layer away from the substrate; wherein the solder pads comprise a first conductive structure and the bonding pins comprise a second conductive structure; the first conductive structure is located in the second conductive layer and the second conductive structure is located in the first conductive layer”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 1, further comprising: a first conductive layer and a second conductive layer located at a side of the first conductive layer away from the substrate; wherein the solder pads comprise a first conductive structure and the bonding pins comprise a second conductive structure; the first conductive structure is located in the second conductive layer and the second conductive structure is located in the first conductive layer,’ is material to the inventive concept of the application at hand to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Regarding claim 14, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 1, wherein the bonding pins comprise second conductive structures, the light-emitting baseplate further comprises signal traces located in the light-emitting region, one of the signal traces is connected to multiple of the bonding pins; and in the bonding pins connected with the one of the signal traces, second conductive structures of at least two adjacent bonding pins are connected”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 1, wherein the bonding pins comprise second conductive structures, the light-emitting baseplate further comprises signal traces located in the light-emitting region, one of the signal traces is connected to multiple of the bonding pins; and in the bonding pins connected with the one of the signal traces, second conductive structures of at least two adjacent bonding pins are connected,’ is material to the inventive concept of the application at hand to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Claims 6-9, 11-12 and 15 are also objected to due to their dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2024/0237448 A1 (Xu) - A display panel is disclosed including a light-emitting area and a cathode overlapping area, and further includes a first metal layer including a first wire located in the cathode overlapping area, a second metal layer disposed above the first metal layer and including a second wire located in the cathode overlapping area, a third metal layer disposed above the second metal layer and including an extension wire located in the cathode overlapping area, and a light-emitting device disposed above the second metal layer and located in the light-emitting area. The light-emitting device includes an anode layer, an organic functional layer, and a cathode layer in sequence. The cathode layer extends from the light-emitting area to the cathode overlapping area and is connected to the extension wire.
US 2023/0187591 A1 (Tan) - A method is disclosed that includes obtaining a first wafer including a first substrate and epitaxial layers that include a first semiconductor layer, a light-emitting region, and a second semiconductor layer; removing the first substrate from the first wafer to expose the first semiconductor layer; depositing a reflector layer on the first semiconductor layer; forming a first metal bonding layer on the reflector layer; bonding a second metal bonding layer on a backplane wafer to the first metal bonding layer; removing the second substrate to expose the second semiconductor layer; and etching through the second semiconductor layer, the light-emitting region, the first semiconductor layer, the reflector layer, the first metal bonding layer, and the second metal bonding layer to form an array of mesa structures for an array of micro-light emitting diodes.
US 2022/0393087 A1 (Zeng) - A display substrate is disclosed including a base substrate including a display area and a bonding area; a first metal conductive layer pattern on the base substrate; a first passivation layer on the first metal conductive layer pattern; a second metal conductive layer pattern on the first passivation layer; a second passivation layer on the second metal conductive layer pattern; a first blackening layer pattern is disposed between the first metal conductive layer pattern and the first passivation layer, an orthographic projection of which on the base substrate is located in that of the first metal conductive layer pattern on the base substrate; and/or a second blackening layer pattern is disposed between the second metal conductive layer pattern and the second passivation layer, an orthographic projection of which on the base substrate is located in that of the second metal conductive layer pattern on the base substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
05/29/2026
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