DETAILED ACTION
This office action is in response to the amendment filed on 09/03/2026.
Currently claims 1-16 are pending in the application. Claim 4 has been amended. Claims 1-16 are examined in this Office action.
Response to Amendment
The amendment filed on 09/03/2026 has been entered. Claim 4 has been amended. No claim has been added or canceled.
The rejection of claims 4-9 under 35 U.S.C. 112(b) is withdrawn in view of the amendment to claim 4.
Response to Arguments
Applicant’s arguments filed on 09/03/2026 have been fully considered but they are not persuasive.
Item #1
Issue raised - Applicant argued (Remarks, pages 6-7) that Yao fails to disclose “wherein the first insulation layer is provided with first openings located in the bonding region, and an orthographic projection of each of the first openings on the substrate is within an orthographic projection of one of the bonding pins on the substrate.”
Applicable rule - MPEP 2125(I); In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972).
Analysis – First, Applicant argues that Yao’s written description is silent on the claimed projection relationship. The examiner respectfully disagrees. Drawings can anticipate a claim if they clearly show the structure which is claimed. See MPEP 2125(I); In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). Claim 1 recites no dimension or proportion; it recites only a containment relationship between the first openings and the bonding pins, which Yao’s Fig. 1 clearly shows, as explained below. Moreover, Yao’s written description is consistent with Fig. 1: Yao states that the protective layer (50) exposes the oxidation protection layer (3) (pages 5-6), which is located on the side of the second pad (4) away from the base substrate (1) (pages 5-6), and that the fourth flat layer (30) covers the area between the second pads (4) (pages 5-6). Thus, the opening in the protective layer (50) exposes the surface of the bonding pin (4), while the area outside the bonding pins (4) remains covered.
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Second, Applicant argues that Fig. 1, at best, shows that the opening overlaps the underlying bonding pin, and that “overlap” is not “within.” The examiner respectfully disagrees. As shown in Yao’s Fig. 1 (as annotated in the rejection below), the first insulation layer (50) extends over and covers both opposite edge portions of the bonding pin (4), and both sidewalls of the opening terminate inboard of the edges of the bonding pin (4); the oxidation protection layer (3) is exposed only within the opening. Fig. 1 therefore shows the opening bounded within the bonding pin (4), not merely overlapping it. Applicant has provided no evidence that the opening of Yao extends beyond the bonding pin (4), and arguments of counsel cannot take the place of evidence in the record. See MPEP 2145(I).
Conclusions - Accordingly, the rejection of claims 1, 3, 13 and 16 under 35 U.S.C. 102(a)(1) over Yao is maintained. Applicant’s amendment to claim 4 necessitated the new ground of rejection of claim 4 under 35 U.S.C. 102(a)(1) over Yao set forth below; accordingly, the previous rejection of claim 4 under 35 U.S.C. 103 is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 13 and 16 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by CN 113964112 A (Yao).
Regarding claim 1, Yao discloses, a light-emitting baseplate (as annotated on Fig. 1; pages 5-6), comprising a bonding region (A2) and a light-emitting region (A1), wherein the light-emitting baseplate comprises:
a substrate (1; pages 5-6);
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solder pads (2 and 2’; pages 5-6), located on the substrate (1) and in the light-emitting region (A1), wherein the light-emitting region (A1) comprises two layers (5 and 2’) of conductive structure (Fig. 1; pages 5-6);
bonding pins (4), located on the substrate (1) and in the bonding region (A2), wherein the bonding region (A2) comprises one layer (layer of bonding pad 4) of conductive structure (Fig. 1; pages 5-6); and
a first insulation layer (50), located at a side of the bonding pins (4) away from the substrate (1), wherein the first insulation layer (50) is provided with first openings (as annotated on Fig. 1, there will be plurality of openings since the device would have many light-emitting baseplates) located in the bonding region (A2) (Fig. 1; pages 5-6), and
an orthographic projection of each of the first openings (as annotated on Fig. 1) on the substrate (1) is within an orthographic projection of one of the bonding pins (4) on the substrate (1) (Fig. 1; pages 5-6).
Regarding claim 3, Yao discloses, the light-emitting baseplate according to claim 1, wherein the first insulation layer (50) comprises an inorganic layer (silicon nitride, silicon oxide; page 10) located in the bonding region (A2).
Regarding claim 4, Yao discloses, the light-emitting baseplate according to claim 1, comprising:
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a first conductive layer (5; first wiring layer, including anode wiring 54 and cathode wiring 55; Figs. 1, 5; page 9) in the light-emitting region (A1) and a second conductive layer (second wiring layer including first pads 2 and 2’, second pad 4 and traces 11 and 12, “arranged in the same layer”; Figs. 1, 5; page 9) in the light-emitting region (A1) and the bonding region (A2), wherein a part (portion including first pads 2 and 2’; Fig. 1) of the second conductive layer in the light-emitting region (A1) is located at a side of the first conductive layer (5) away from the substrate (1) (Fig. 1; pages 5-6);
wherein the solder pads (2 and 2’) comprise a first conductive structure (as annotated on Fig. 1) and the bonding pins (4) comprise a second conductive structure (portion of the second wiring layer forming second pad 4; Fig. 1); and
the first conductive structure (as annotated on Fig. 1) is located in the part of the second conductive layer in the light-emitting region (A1) and the second conductive structure (second pad 4) is located in a part of the second conductive layer in the bonding region (A2) (the second pad 4 and the first pads 2, 2’ are in the same film layer, formed by one patterning process; Fig. 1; pages 5 and 9).
Regarding claim 13, Yao discloses, the light-emitting baseplate according to claim 1, wherein the bonding pins (4) comprise a second conductive structure (as annotated on Fig. 1) and second conductive structures of adjacent bonding pins are spaced apart (with multiple light emitting devices, the second conductive structures would obviously be spaced apart).
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Regarding claim 16, Yao discloses, a display apparatus (light emitting system with plurality of light emitting baseplate of Fig. 1; pages 4-5), comprising the light-emitting baseplate according to claim 1 (see the rejection of claim 1).
Allowable Subject Matter
Claims 2, 5-12 and 14-15 are objected to as being dependent upon rejected base claims but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 2, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 1, further comprising: a flux layer partially located in the first openings, and the flux layer has a thickness greater than a thickness of a part of the first insulation layer in the bonding region”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 1, further comprising: a flux layer partially located in the first openings, and the flux layer has a thickness greater than a thickness of a part of the first insulation layer in the bonding region,’ is material to the inventive concept of the application at hand to use flux layer to bond the bonding pins to the FPC during secondary soldering so as to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Regarding claim 5, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 4, further comprising: a transition region between the bonding region and the light-emitting region, wherein the transition region is provided with a connection trace located in the first conductive layer, and the light-emitting region is provided with a signal trace connected with the connection trace; and the second conductive layer comprises a connection portion located in the transition region, the connection portion is connected with the second conductive structure, and the connection portion is partially located at a side of the connection trace away from the substrate and is connected with the connection trace”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 4, further comprising: a transition region between the bonding region and the light-emitting region, wherein the transition region is provided with a connection trace located in the first conductive layer, and the light-emitting region is provided with a signal trace connected with the connection trace; and the second conductive layer comprises a connection portion located in the transition region, the connection portion is connected with the second conductive structure, and the connection portion is partially located at a side of the connection trace away from the substrate and is connected with the connection trace,’ is material to the inventive concept of the application at hand to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Regarding claim 10, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 1, further comprising: a first conductive layer and a second conductive layer located at a side of the first conductive layer away from the substrate; wherein the solder pads comprise a first conductive structure and the bonding pins comprise a second conductive structure; the first conductive structure is located in the second conductive layer and the second conductive structure is located in the first conductive layer”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 1, further comprising: a first conductive layer and a second conductive layer located at a side of the first conductive layer away from the substrate; wherein the solder pads comprise a first conductive structure and the bonding pins comprise a second conductive structure; the first conductive structure is located in the second conductive layer and the second conductive structure is located in the first conductive layer,’ is material to the inventive concept of the application at hand to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Regarding claim 14, the closest prior art, CN 113964112 A (Yao), in conjunction with, and in combination with the other claimed features, fails to disclose, “the light-emitting baseplate according to claim 1, wherein the bonding pins comprise second conductive structures, the light-emitting baseplate further comprises signal traces located in the light-emitting region, one of the signal traces is connected to multiple of the bonding pins; and in the bonding pins connected with the one of the signal traces, second conductive structures of at least two adjacent bonding pins are connected”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the light-emitting baseplate according to claim 1, wherein the bonding pins comprise second conductive structures, the light-emitting baseplate further comprises signal traces located in the light-emitting region, one of the signal traces is connected to multiple of the bonding pins; and in the bonding pins connected with the one of the signal traces, second conductive structures of at least two adjacent bonding pins are connected,’ is material to the inventive concept of the application at hand to solve the problem of inability to perform secondary soldering using the solder pad, thereby increasing the product yield.
Claims 6-9, 11-12 and 15 are also objected to due to their dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2024/0237448 A1 (Xu) - A display panel is disclosed including a light-emitting area and a cathode overlapping area, and further includes a first metal layer including a first wire located in the cathode overlapping area, a second metal layer disposed above the first metal layer and including a second wire located in the cathode overlapping area, a third metal layer disposed above the second metal layer and including an extension wire located in the cathode overlapping area, and a light-emitting device disposed above the second metal layer and located in the light-emitting area. The light-emitting device includes an anode layer, an organic functional layer, and a cathode layer in sequence. The cathode layer extends from the light-emitting area to the cathode overlapping area and is connected to the extension wire.
US 2023/0187591 A1 (Tan) - A method is disclosed that includes obtaining a first wafer including a first substrate and epitaxial layers that include a first semiconductor layer, a light-emitting region, and a second semiconductor layer; removing the first substrate from the first wafer to expose the first semiconductor layer; depositing a reflector layer on the first semiconductor layer; forming a first metal bonding layer on the reflector layer; bonding a second metal bonding layer on a backplane wafer to the first metal bonding layer; removing the second substrate to expose the second semiconductor layer; and etching through the second semiconductor layer, the light-emitting region, the first semiconductor layer, the reflector layer, the first metal bonding layer, and the second metal bonding layer to form an array of mesa structures for an array of micro-light emitting diodes.
US 2022/0393087 A1 (Zeng) - A display substrate is disclosed including a base substrate including a display area and a bonding area; a first metal conductive layer pattern on the base substrate; a first passivation layer on the first metal conductive layer pattern; a second metal conductive layer pattern on the first passivation layer; a second passivation layer on the second metal conductive layer pattern; a first blackening layer pattern is disposed between the first metal conductive layer pattern and the first passivation layer, an orthographic projection of which on the base substrate is located in that of the first metal conductive layer pattern on the base substrate; and/or a second blackening layer pattern is disposed between the second metal conductive layer pattern and the second passivation layer, an orthographic projection of which on the base substrate is located in that of the second metal conductive layer pattern on the base substrate.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
10/12/2026
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