Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
Number of figures submitted does not match the number of figures listed under Brief Description of Drawings in the specification. All of the figures with alphabets should be listed separately. For example, ‘Figs. 1A-1C’ should be ‘Figs. 1A, 1B and 1C’.
In particular, in the ‘Brief description of the drawings’:
‘Fig. 4A-4C’, ‘Fig. 5A-5C’, ‘Fig. 6A-6C’, ‘Fig. 8A-8C’, ‘Fig. 9A-9C’ and ‘Fig. 11A-11C’ are objected.
See MPEP 500 - Receipt and Handling of Mail and Papers, MPEP 507 - Drawing Review in the Office of Patent Application Processing (OPAP). This labeling convention ensures clarity and consistency in referencing figures throughout the patent application and publication. Improper labeling may result in an objection from OPAP and require correction.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Fig 1A: 1181, 1182.
Fig 7: 700, 702, 704, 706
Fig 10: 1000, 1004, 1006, 1014, 1010
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application.
Furthermore, the drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
In Fig 2B, no labels are provided for structural elements. Every structural element or feature of the invention described in the specification must be shown in the drawings and, to ensure clarity, should be labeled with reference numerals that correspond directly to the written description.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application.
Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4 and 15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 4, the claim recites the limitation “the source and drain region regions” in line(s) 3. There is insufficient antecedent basis for this limitation in the claim because the claim 1 recites a "source and a drain," but not "source and drain regions". While seemingly minor, the change in terminology creates ambiguity as to whether these are the same structures. Also, there is a typographical error ("region regions"). Thus, the examiner recommends amending the limitation to “the source and drain
Regarding claim 15, the claim recites the limitation “the conductive island” in line 4. But the independent claim 14 never defines a "conductive island". It defines a "quantum dot." While a quantum dot acts as an island, the legal term of art must be consistent. Thus, the examiner recommends amending the limitation to “a quantum dot” as disclose in the [0014] of the SPEC.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8, 11-12 and 14-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fogarty (US 20220223779).
Regarding claim 1. Fig 4 (a plan view of a processor element), Fig 5 (a cross-section view of Fig 4), Fig 6 (a cross-section view of Fig 4) and Fig 9 (an array of processor elements) of Fogarty disclose Integrated quantum dot structure comprising:
one or more semiconductor layers 110 arranged on a substrate (Figs 5-6, [0012]/[0055]: Fogarty discloses a processor element comprising a silicon layer (110), which may be an epitaxial layer grown on a conventional silicon substrate);
a single electron tunneling (SET) transistor formed in or over the one or more semiconductor layers, the SET transistor comprising a source and a drain connected by tunneling junctions (Fig 5: in the oxide layer 104) to a conductive island (Fig 5, [0025], [0058]-[0059]: Fogarty discloses a SET formed in the silicon layer comprising a conductive island (118) located between tunneling junctions (formed in the oxide layer 104) which are connected to the source and drain electrodes (specifically, the ohmic regions 116A and 116B);
a plurality of quantum dot regions arranged around the SET transistor, the plurality of quantum dot regions being formed in the one or more semiconductor layers (Fig 6, [0035], [0050], [0065]: Fogarty discloses a second quantum dot (120) and neighboring dots in adjacent processor elements, capacitively influencing the SET) and
the SET transistor being capacitively coupled to the plurality of quantum dot regions and being configured to readout the plurality of quantum dot regions (Fig 5, [0065]: Fogarty discloses that the SET island (118) can read out the state of the second quantum dot (120) via the Pauli spin-blockade mechanism and changes in total capacitance, thereby disclosing capacitive coupling to enable readout);
one or more insulating layers provided over the SET transistor and the quantum dot regions (Figs 5-6, [0057], [0063]: Fogarty discloses a thick oxide material (102) and a dielectric gate layer (104) provided over and surrounding the SET island and quantum dot regions);
a source electrode and a drain electrode arranged over the one or more insulating layers (Fig 5, [0056], [0058]: Fogarty discloses metal source and drain electrodes (112A, 112B) arranged above the insulating layers of the processor element); and,
first and second nano-scale metallic vias 114A/114B connecting the source and drain of the SET transistor to the source and drain electrodes over the one or more insulating layers respectively (Fig 5, [0012], [0056]: Fogarty discloses metal vias (114A, 114B) connecting the SET source/drain to the overlying electrodes. These vias are defined as having an interface cross-sectional area ≤100 nm × 100 nm, thereby meeting the nano-scale requirement).
Regarding claim 2. Fogarty discloses The integrated quantum dot structure according to claim 1 further comprising:
a third nano-scale metallic via connecting a plunger electrode that is capacitively connected to the conductive island to a gate electrode arranged over the one or more insulating layers (Figs. 5–6, [0025], [0057]–[0060]: Fogarty further discloses a gate electrode (106A/106B) arranged in an upper metallization layer over one or more insulating layers, including a thick oxide layer (102) and a dielectric gate layer (104) (Fig 5, [0056]–[0058]; Fig. 5). Additionally, Fogarty discloses nano-scale metallic vias (e.g., 108A, 108B) having cross-sectional dimensions on the order of 100 nm or less, which vertically connect lower-level electrodes to overlying gate electrodes (Fig 5, [0056]).
Regarding claim 3. Fogarty discloses The integrated quantum dot structure according to claim 1 wherein the SET transistor is formed in the one or more semiconductor layers (Figs. 5–6, [0012], [0025], [0055], [0058]–[0059]: Fogarty explicitly describes the SET island and associated tunneling regions as being defined in the silicon layer grown on the substrate).
Regarding claim 4. Fogarty discloses The integrated quantum dot structure according to claim 3 wherein the conductive island is a quantum dot region formed in the one or more semiconductor layers and wherein the source and drain region regions of the SET are formed in the one or more semiconductor layers (Figs. 5–6, [0012], [0025], [0035], [0050], [0058]–[0059]: Fogarty explicitly treats the SET island as a quantum-confined region and describes the source and drain as doped semiconductor regions adjacent to the island).
Regarding claim 5. Fogarty discloses The integrated quantum dot structure according to claim 3 wherein one end of the first nano-scale metallic via and one end of the second nano-scale metallic via form ohmic contacts with the one or more semiconductor layers (Fig. 5, [0012], [0056], [0058]: Fogarty discloses nano-scale metallic vias that vertically connect overlying metal electrodes to ohmic regions (e.g., 116A, 116B) formed in the semiconductor layer. Fogarty further teaches that these regions are ohmic contact regions between the semiconductor layer and the metal interconnects, thereby inherently and explicitly forming ohmic contacts at the ends of the vias).
Regarding claim 8. Fogarty discloses The integrated quantum dot structure according to claim 1 wherein quantum dot regions in the plurality of quantum dot regions are separated by barrier regions (Figs 6, 9, [0035], [0050], [0065]: The tunneling barriers are inherent to Fogarty’s quantum dot array architecture and physically separate adjacent quantum dots).
Regarding claim 11. Fogarty discloses The integrated quantum dot structure according to claim 1 wherein the plurality of quantum dot regions forms a 2D array of quantum dot regions (Fig 9, [0084]) or a 3D array of quantum dot regions.
Regarding claim 12. Fogarty discloses The integrated quantum dot structure according to claim 1 wherein cross-sectional dimensions of the first and second nano-scale metallic vias are selected between 500 and 10 nm ([0012], [0056]: 100 nm).
Regarding claim 14. Fig 4 (a plan view of a processor element), Fig 5 (a cross-section view of Fig 4), Fig 6 (a cross-section view of Fig 4) and Fig 9 (an array of processor elements) of Fogarty disclose A single electron tunneling (SET) quantum dot readout structure comprising:
one or more semiconductor layers 110 arranged on a substrate (Figs 5-6, [0012]/[0055]: Fogarty discloses a processor element comprising a silicon layer (110), which may be an epitaxial layer grown on a conventional silicon substrate);
a quantum dot (Fig 5, [0065]: 118 a first quantum dot (acting as the SET island 118)) connected by tunnel junctions to a source area and a drain area, the quantum dot, the tunnel junctions and the source area and drain area (116A, 116B) forming a SET transistor being formed in or over the one or more semiconductor layers 110 (Fig 5, [0065]);
the SET transistor being configured to read out a plurality of quantum dot structures arranged around the SET transistor (Fig 6, [0035], [0050], [0065]: Fogarty discloses a second quantum dot (120) and neighboring dots in adjacent processor elements, capacitively influencing the SET) and formed in the one or more semiconductor layers, the SET transistor being capacitively coupled to the a plurality of quantum dot regions (Fig 5, [0065]: Fogarty discloses that the SET island (118) can read out the state of the second quantum dot (120) via the Pauli spin-blockade mechanism and changes in total capacitance, thereby disclosing capacitive coupling to enable readout);
one or more insulating layers provided over the SET transistor (Figs 5-6, [0057], [0063]: Fogarty discloses a thick oxide material (102) and a dielectric gate layer (104) provided over and surrounding the SET island and quantum dot regions);
a source electrode and a drain electrode arranged over the one or more insulating layers (Fig 5, [0056], [0058]: Fogarty discloses metal source and drain electrodes (112A, 112B) arranged above the insulating layers of the processor element); and,
first and second nano-scaled metallic vias 114A/114B connecting the source area and drain area of the SET transistor to the source electrode and drain electrode over the one or more insulating layers respectively (Fig 5, [0012], [0056]: Fogarty discloses metal vias (114A, 114B) connecting the SET source/drain to the overlying electrodes. These vias are defined as having an interface cross-sectional area ≤100 nm × 100 nm, thereby meeting the nano-scale requirement).
Regarding claim 15. Fogarty discloses The quantum dot readout structure according to claim 14 further comprising:
a third nano-scale metallic via connecting a plunger electrode that is capacitively connected to the conductive island to a gate electrode arranged over the one or more insulating layers (Figs. 5–6, [0025], [0057]–[0060]: Fogarty further discloses a gate electrode (106A/106B) arranged in an upper metallization layer over one or more insulating layers, including a thick oxide layer (102) and a dielectric gate layer (104) (Fig 5, [0056]–[0058]; Fig. 5). Additionally, Fogarty discloses nano-scale metallic vias (e.g., 108A, 108B) having cross-sectional dimensions on the order of 100 nm or less, which vertically connect lower-level electrodes to overlying gate electrodes (Fig 5, [0056]).
Regarding claim 16. Fogarty discloses The quantum dot readout structure according to claim 14 wherein the SET transistor is formed in the one or more semiconductor layers (Figs. 5–6, [0012], [0025], [0055], [0058]–[0059]: Fogarty explicitly describes the SET island and associated tunneling regions as being defined in the silicon layer grown on the substrate) or wherein the SET transistor is formed in a metallic or doped layer formed over the one or more semiconductor layers.
Regarding claim 17. Fogarty discloses The quantum dot readout structure according to claim 14 wherein the cross-sectional dimensions of the first and second nano-scale metallic vias are selected between 400 and 20 nm ([0012], [0056]: 100 nm).
Regarding claim 18. Fogarty discloses The integrated quantum dot structure according to claim 5, wherein the ohmic contacts comprise nano-scale ohmic contacts (Fig 5, [0012], [0056]: Fogarty discloses SET source/drain electrodes connected to the semiconductor layer via metallic vias 114A/114B, and the cross-sectional area of these vias is ≤100 nm × 100 nm, which qualifies as nano-scale. Ohmic contact is explicitly described where the vias connect the SET source/drain to the overlying electrodes).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Fogarty (US 20220223779) in view of Jock (US 10482388).
Regarding claim 6. Fogarty discloses The integrated quantum dot structure according to claim 1. But Fogarty does not disclose wherein the SET transistor is formed in a metallic or doped layer formed over the one or more semiconductor layers.
However, Jock discloses SET transistor is formed in a metallic or doped layer 220 (col 10, line 16) formed over the one or more semiconductor layers 210 (col 10, line 16) (Fig 2B).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Fogarty’s device to have Jock’s structure for the purpose of providing high-temperature operability, CMOS compatibility, and cost-effective fabrication.
Regarding claim 7. Fogarty in view of Jock discloses The integrated quantum dot structure according to claim 6, Fogarty discloses wherein a first metallic via 114A connects the source electrode with the source of the SET transistor and wherein a second metallic via 114B connects the drain electrode with the drain of the SET transistor [0056].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Fogarty (US 20220223779) in view of Pioro-Ladriere (US 10929769).
Regarding claim 9. Fogarty discloses The integrated quantum dot structure according to claim 8 further comprising:
a barrier electrode structure (Fig 6: electrodes positioned between 112A and 106A and between 112B and 106B are arranged over the quantum dot structure to influence the SET island (118) and neighboring quantum dots) comprising:
a first barrier electrode (electrode between 112A and 106A) arranged in one direction over the quantum dot structure (arranged in one direction over the quantum dot structure);
a second barrier electrode (electrode between 112B and 106B) arranged in a second direction over the quantum dot structure (arranged in a different direction over the quantum dot structure).
But Fogarty does not disclose the first barrier electrode and second barrier electrode crossing each other at a first barrier region selected from the barrier regions, the first and second barrier electrode forming a barrier electrode pair for controlling a coupling between a first quantum dot and a second quantum dot separated by the first barrier region.
However, Pioro-Ladriere (Fig. 3A, [0014]) discloses a quantum dot device architecture with multiple electrodes (barrier/control gates) arranged over quantum dot regions to define tunnel barriers and control coupling. The electrodes are arranged in different directions, forming a crossbar-style grid, which allows localized control of tunneling between quantum dots. Adjusting the potentials on these electrodes enables precise control of the tunnel barrier and coupling between neighboring quantum dots. This teaches the functional concept of a barrier electrode pair crossing a barrier region to control inter-dot coupling, as recited in the claim 9.
It would have been obvious to a person of ordinary skill in the art to modify Fogarty’s electrode arrangement based on Pioro-Ladriere to provide crossing barrier electrodes for enhanced 2D inter-dot coupling control. This combination is motivated by the need for precise 2D control in a quantum dot array, which Fogarty explicitly discloses as a 2D array of processor elements (Fig. 9), and by standard industry practice of using crossing electrodes to minimize control line fan-out. Accordingly, claim 9 is unpatentable over Fogarty in view of Pioro-Ladriere.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fogarty (US 20220223779).
Regarding claim 10. Fogarty discloses The integrated quantum dot structure according to claim 1. But Fogrty does not explicitly disclose wherein the dimensions of the quantum dot regions are selected between 200 and 20 nm.
However, Fogarty discloses nano-scale quantum dot regions necessary for SET and qubit functionality [0065].
Therefore, a person of ordinary skill in the art would recognize that the specific dimensions of the quantum dot regions must be selected within an effective range to achieve proper quantum behavior, including tunneling, inter-dot capacitive coupling, and reliable readout. And selecting quantum dot dimensions between 20 and 200 nm is a predictable design choice based on conventional nano-fabrication constraints and the requirements for quantum confinement.
While the claim does not explicitly recite that the range is critical, it is apparent to one of ordinary skill in the art that choosing dimensions outside this range would reduce device operability. The skilled artisan would therefore select dimensions within the claimed 20–200 nm range as a matter of design effectiveness.
Accordingly, it would have been obvious to one of ordinary skill in the art to select Fogarty’s nano-scale quantum dot regions to fall within the claimed 20–200 nm range to achieve an operable integrated quantum dot structure as recited in the claim 10.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Fogarty (US 20220223779) in view of Pioro-Ladriere (US 10929769), and further in view of Roberts (US 20190273197).
Regarding claim 19. Fogarty in view of Pioro-Ladriere discloses The integrated quantum dot structure according to claim 9. But Fogarty in view of Pioro-Ladriere does not disclose wherein the barrier electrodes and/or the first and second nano-scale metallic vias are made of metal that becomes superconductive below a critical temperature.
However, Roberts discloses quantum computing devices that include superconducting circuit elements, including superconducting conductive pathways and electrodes, formed from metals that become superconductive below a critical temperature ([0071]: metals such as aluminum, niobium, or related superconducting materials are used for electrodes, interconnects, and conductive paths; [0085]: in quantum devices operating at cryogenic temperatures, because such materials reduce dissipation and noise. Thus, Roberts expressly teaches using superconducting metals for electrodes and conductive interconnects in quantum systems).
Therefore, Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the barrier electrodes and/or nano-scale metallic vias of Fogarty in view of Pioro-Ladriere to have the superconducting metals of Roberts for the purpose of reducing resistive losses; minimizing thermal noise; enhancing charge and coupling stability in quantum dot devices; and compatibility with cryogenic operation, which is essential to quantum dot readout and control. Such substitution of one known conductive material with another known, functionally advantageous conductive material (superconducting metal) in a known quantum device structure represents a predictable use of prior-art elements according to their established functions.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fogarty (US 20220223779) in view of Hutin (US 20180331108; in the IDS on 1/31/24).
Regarding claim 20. Fogarty discloses The integrated quantum dot structure according to claim 1. But Fogarty does not disclose wherein the one or more semiconductor layers include a semiconductor heterostructure, a MOS structure, a semiconductor-on-insulator structure, or geometries comprising finFET. nanowires, hut wire, or self-assembled structures.
However, Fig 4 of Hutin discloses the one or more semiconductor layers (148) include a semiconductor heterostructure, a MOS structure, a semiconductor-on-insulator structure ([0084]/[0085]: 148 is polycrystalline silicon and 153 is insulator), or geometries comprising finFET. nanowires, hut wire, or self-assembled structures.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Fogarty’s device to have the Hutin’s structure for the purpose of providing enhanced electrical isolation, significantly reducing leakage current and parasitic capacitance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Changhyun Yi/Primary Examiner, Art Unit 2812