DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 2 and 3 are objected to because of the following informalities:
1. A semiconductor device comprising:
a display portion, wherein the display portion comprises a plurality of subpixels, wherein each of the plurality of subpixels comprises a first transistor, a second transistor, a first capacitor, a second capacitor, a third capacitor, a first insulating layer, and a wiring,
wherein the first transistor is electrically connected to the second transistor, the first capacitor, the second capacitor, and the third capacitor,
wherein each of the first capacitor, the second capacitor and
wherein the first conductive layers of the first capacitor, the second capacitor,
wherein in a top view, a proportion of a total area of the first conductive layers of the first capacitor, the second capacitor,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor.
Appropriate correction is required.
2. A semiconductor device comprising:
a display portion, wherein the display portion comprises a plurality of subpixels and a substrate, wherein each of the plurality of subpixels comprises a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a third capacitor, a first insulating layer, and a wiring,
wherein each of the first transistor, second transistor,
wherein the third transistor is electrically floating,
wherein each of the first capacitor, the second capacitor and
wherein the first insulating layer is provided over the first transistor and the second transistor,
wherein the first conductive layers of the first capacitor, the second capacitor,
wherein in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to15%,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor,
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor,
wherein each of the first transistor, the second transistor and
wherein in the top view, a proportion of a total area of the semiconductor layers of the first transistor, the second transistor and
Appropriate correction is required.
3. A semiconductor device comprising:
a display portion, wherein the display portion comprises a plurality of subpixels and a substrate, wherein each of the plurality of subpixels comprises a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a third capacitor, a first insulating layer, and a wiring,
wherein each of the first transistor, second transistor,
wherein the third transistor is electrically floating,
wherein each of the first capacitor, the second capacitor and
wherein the first insulating layer is provided over the first transistor and the second transistor,
wherein the first conductive layers of the first capacitor, the second capacitor,
wherein in a top view, a proportion of a total area of the first conductive layers of the first capacitor, the second capacitor, the third capacitor and the wiring to an area of the subpixel is greater than or equal to15%,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor,
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor,
wherein each of the first transistor, the second transistor and
wherein the semiconductor layer of the third transistor comprises a region shared with the semiconductor layer of the first transistor, and
wherein in the top view, a proportion of a total area of the semiconductor layers of the first transistor, the second transistor and
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. JP2016042202A.
Regarding claim 1, Kubota et al. in Figs. 1, 11-13 and [0006]-[0091] discloses a semiconductor device 10 comprising:
a display portion 100, Fig. 2,
wherein the display portion comprises a plurality of subpixels, wherein each of the plurality of subpixels comprises a first transistor 42P, a second transistor 34P, a first capacitor 44, a second capacitor 411, a third capacitor 412, a first insulating layer 180, and a wiring 184, Figs. 11-13,
wherein the first transistor 42P is electrically connected to the second transistor 34P, the first capacitor 44, the second capacitor 411, and the third capacitor 412,
wherein each of the first capacitor to the third capacitor 44, 411, 412 comprises a first conductive layer 44(194), 411(411a), 412(412a), a second conductive layer 44(195), 411(411b), 412(412b) and a second insulating layer 44(190), 411(190), 412(210) sandwiched between the first conductive layer and the second conductive layer [0068]-[0071],
wherein the first insulating layer 180 is provided over the first transistor 42P and the second transistor 34P,
wherein the first conductive layers of the first capacitor to the third capacitor 44(194), 411(411a), 412(412a), and the wiring 184 are each provided over the first insulating layer 180.
Kubota et al. does not expressly disclose wherein in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor.
Applicant has not disclosed that in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor.
However, Kubota et al. teaches in [0006], [0008], [0010], [0068]-[0070] and [0072] teaches that the arrangement of the capacitors in the electro-optical device viewed in a direction perpendicular to the first main surface achieve a large capacitance value with a small area. As a result, the ratio of the area of the pixel circuit to the substrate can be increased. This demonstrates that to achieve large capacitance the area of the conductive layers of the capacitors and the wiring would be considered result effective variables.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the area of the capacitors and wiring in order “to increase the capacitance and improve the device performance” thereof and optimize “in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor” as “result effective variables”, and arrives at the recited limitation.
Claim(s) 2, 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. JP2016042202A in view of Lim et al. US 2022/0020328.
Regarding claim 2, Kubota et al. in Figs. 1, 11-13 and [0006]-[0091] discloses a semiconductor device 10 comprising:
a display portion 100, Fig. 2,
wherein the display portion comprises a plurality of subpixels, wherein each of the plurality of subpixels comprises a first transistor 42P, a second transistor 34P, a first capacitor 44, a second capacitor 411, a third capacitor 412, a first insulating layer 180, and a wiring 184, Figs. 11-13,
wherein the first transistor 42P is electrically connected to the second transistor 34P, the first capacitor 44, the second capacitor 411, and the third capacitor 412,
wherein each of the first capacitor to the third capacitor 44, 411, 412 comprises a first conductive layer 44(194), 411(411a), 412(412a), a second conductive layer 44(195), 411(411b), 412(412b) and a second insulating layer 44(190), 411(190), 412(210) sandwiched between the first conductive layer and the second conductive layer [0068]-[0071],
wherein the first insulating layer 180 is provided over the first transistor 42P and the second transistor 34P,
wherein the first conductive layers of the first capacitor to the third capacitor 44(194), 411(411a), 412(412a), and the wiring 184 are each provided over the first insulating layer 180.
Kubota et al. does not expressly disclose wherein in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor.
Applicant has not disclosed that in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor.
However, Kubota et al. teaches in [0006], [0008], [0010], [0068]-[0070] and [0072] teaches that the arrangement of the capacitors in the electro-optical device viewed in a direction perpendicular to the first main surface achieve a large capacitance value with a small area. As a result, the ratio of the area of the pixel circuit to the substrate can be increased. This demonstrates that to achieve large capacitance the area of the conductive layers of the capacitors and the wiring would be considered result effective variables.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the area of the capacitors and wiring in order “to increase the capacitance and improve the device performance” thereof and optimize “in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor” as “result effective variables”, and arrives at the recited limitation.
Kubota et al. does not expressly disclose a third transistor provided over the substrate and electrically floating, wherein each of the first transistor to the third transistor comprises a semiconductor layer, and wherein in the top view, a proportion of a total area of the semiconductor layers of the first transistor to the third transistor to the area of the subpixel is greater than or equal to 15 %.
However, in analogous art, Lim et al. in Figs. 3, 5, 8 and [0089]-[0134] teaches a display device capable of reducing a leakage current that includes a first transistor, second transistor and a dummy (i.e. third) transistor and semiconductor layers which form the active areas of the transistors [0156].
Lim et al. does not expressly teach wherein in the top view, a proportion of a total area of the semiconductor layers of the first transistor to the third transistor to the area of the subpixel is greater than or equal to 15 %.
Lim et al. teaches that when two gate electrodes are connected to each other having the same potential the channel length may be elongated which may increase the resistance and the leakage current may be reduced to secure the stability of an operation. This demonstrates that to achieve increased resistance and reduced leakage current the area of the channel (i.e. semiconductor layer) would be considered result effective variables.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the area of the semiconductor layers in order “to reduce leakage current and improve the device performance” thereof and optimize “a proportion of a total area of the semiconductor layers of the first transistor to the third transistor to the area of the subpixel is greater than or equal to 15 %” as “result effective variables”, and arrives at the recited limitation.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lim et al. in the semiconductor device of Kubota et al. for the purpose of reducing leakage current.
Regarding claim 3, Kubota et al. in Figs. 1, 11-13 and [0006]-[0091] discloses a semiconductor device 10 comprising:
a display portion 100, Fig. 2,
wherein the display portion comprises a plurality of subpixels, wherein each of the plurality of subpixels comprises a first transistor 42P, a second transistor 34P, a first capacitor 44, a second capacitor 411, a third capacitor 412, a first insulating layer 180, and a wiring 184, Figs. 11-13,
wherein the first transistor 42P is electrically connected to the second transistor 34P, the first capacitor 44, the second capacitor 411, and the third capacitor 412,
wherein each of the first capacitor to the third capacitor 44, 411, 412 comprises a first conductive layer 44(194), 411(411a), 412(412a), a second conductive layer 44(195), 411(411b), 412(412b) and a second insulating layer 44(190), 411(190), 412(210) sandwiched between the first conductive layer and the second conductive layer [0068]-[0071],
wherein the first insulating layer 180 is provided over the first transistor 42P and the second transistor 34P,
wherein the first conductive layers of the first capacitor to the third capacitor 44(194), 411(411a), 412(412a), and the wiring 184 are each provided over the first insulating layer 180.
Kubota et al. does not expressly disclose wherein in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor.
Applicant has not disclosed that in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor.
However, Kubota et al. teaches in [0006], [0008], [0010], [0068]-[0070] and [0072] teaches that the arrangement of the capacitors in the electro-optical device viewed in a direction perpendicular to the first main surface achieve a large capacitance value with a small area. As a result, the ratio of the area of the pixel circuit to the substrate can be increased. This demonstrates that to achieve large capacitance the area of the conductive layers of the capacitors and the wiring would be considered result effective variables.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the area of the capacitors and wiring in order “to increase the capacitance and improve the device performance” thereof and optimize “in a top view, a proportion of a total area of the first conductive layers of the first capacitor to the third capacitor and the wiring to an area of the subpixel is greater than or equal to 15 %,
wherein an area of the first conductive layer of the second capacitor is greater than or equal to twice an area of the first conductive layer of the first capacitor, and
wherein an area of the first conductive layer of the third capacitor is greater than or equal to twice the area of the first conductive layer of the first capacitor” as “result effective variables”, and arrives at the recited limitation.
Kubota et al. does not expressly disclose a third transistor provided over the substrate and electrically floating, wherein each of the first transistor to the third transistor comprises a semiconductor layer, wherein the semiconductor layer of the third transistor comprises a region shared with the semiconductor layer of the first transistor, and wherein in the top view, a proportion of a total area of the semiconductor layers of the first transistor to the third transistor to the area of the subpixel is greater than or equal to 15 %.
However, in analogous art, Lim et al. in Figs. 3, 5, 8 and [0089]-[0134] teaches a display device capable of reducing a leakage current that includes a first transistor, second transistor and a dummy (i.e. third) transistor and semiconductor layers which form the active areas of the transistors [0156]. Lim et al. further teaches a channel (i.e. semiconductor layer) of a transistor T3 comprising a region shared with the channel (i.e. semiconductor layer) of a transistor T3-1 creating an elongated channel length.
Lim et al. does not expressly teach wherein in the top view, a proportion of a total area of the semiconductor layers of the first transistor to the third transistor to the area of the subpixel is greater than or equal to 15 %.
Lim et al. teaches that when two gate electrodes are connected to each other having the same potential the channel length may be elongated which may increase the resistance and the leakage current may be reduced to secure the stability of an operation. This demonstrates that to achieve increased resistance and reduced leakage current the area of the channel (i.e. semiconductor layer) would be considered result effective variables.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the area of the semiconductor layers in order “to reduce leakage current and improve the device performance” thereof and optimize “a proportion of a total area of the semiconductor layers of the first transistor to the third transistor to the area of the subpixel is greater than or equal to 15 %” as “result effective variables”, and arrives at the recited limitation.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lim et al. in the semiconductor device of Kubota et al. for the purpose of reducing leakage current.
Regarding claim 6, Kubota et al. in view of Lim et al. teaches the semiconductor device according to any one of claim 3. Kubota et al. teach the semiconductor device further comprising a light-emitting device,
wherein one terminal of the light-emitting device is electrically connected to one of a source and a drain P3 of the first transistor 42P [0007].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. in view of Lim et al. as applied to claim 3 above, and further in view of Shin US 2018/0337288.
Regarding claim 5, Kubota et al. in view of Lim et al. teaches the semiconductor device according to claim 3. Kubota et al. in [0019]-[0032] teaches a driving circuit but does not teach wherein the second transistor is a multi-channel transistor.
Shin teaches in [0040]-[0155] a semiconductor device having improved driving performance and a high-resolution display device with improved display quality that includes a multi-channel transistor.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Shin in the semiconductor device of Kubota et al. and Lim et al. for the purpose of improving the driving performance of the display and providing a high-resolution display device.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. in view of Lim et al. as applied to claim 3 above, and further in view of Kamatani et al. US 2017/0263870.
Regarding claims 7 and 8, Kubota et al. in view of Lim et al. teaches the semiconductor device according claim 3 but does not expressly teach wherein one or more of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor comprise a metal oxide, wherein the metal oxide comprises one or more of indium and zinc.
Kamatani et al. teaches in Fig. 1 and [0145] a display device 1 including an active layer 13 in transistors 18 comprising indium zinc oxide, a transparent conductive oxide known to offer excellent electrical conductivity and optical transparency.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to try IZO as the semiconductor layer of Kubota et al. and Lim et al., as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Allowable Subject Matter
Claims 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, The prior art neither anticipates nor renders obvious, in the context of the claims, wherein a gate of the first transistor is electrically connected to the other terminal of the first capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one terminal of the second capacitor, and one terminal of the third capacitor, wherein a gate of the second transistor is electrically connected to the other terminal of the second capacitor, and wherein a back gate of the second transistor is electrically connected to the other terminal of the third capacitor.
Regarding claim 9, The prior art neither anticipates nor renders obvious, in the context of the claims, wherein the second transistor comprises:
a first conductor and a second conductor placed apart from each other over the semiconductor layer of the second transistor;
a first insulator placed over the first conductor and the second conductor and having an opening formed between the first conductor and the second conductor;
a third conductor placed in the opening of the first conductor; and
a second insulator placed between the third conductor and the semiconductor layer, the first conductor, the second conductor, and the first insulator.
Conclusion
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898