Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. The following title is suggested: “ Method for filling redundant metals in chip, chip for Enhancing Chip Capacitance via Interdigital Redundant Metal Fill and S emiconductor D evice Thereof ” Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim s 3, 5 and 18-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding claim 3 , the claim recites the limitation “ the number of through holes ” in line(s) 3. There is insufficient antecedent basis for this limitation in the claim. The examiner recommends amending the limitation to “[[ the ]] a number of through holes ”. Regarding claim 5 , the claim recites the limitation “ the case” in line(s) 2. There is insufficient antecedent basis for this limitation in the claim. The examiner recommends amending the limitation to “[[ the ]] a case”. Regarding claim 18, the claim recites “ a power source ” and “ a grounding power source ” and the claim 18 i s dependen t on the claim 1. If they are different from the “ a power source ” and “ a grounding power source ” in the claim, they should be properly distinguished. If the are the same, the claim 18 should be amended to “[[ a ]] the power source ” and “[[ a ]] the grounding power source ”. Regarding claim 19 , because of the dependency on claim 1 8 , the claim is also rejected for the reasons set forth above with respect to claim 1 8 . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1 , 18 and 20 are rejected under 35 U.S.C. 102(a)( 1 ) as being anticipated by Ota (US 20050269596 ). Regarding claim 1. Fig 5 of Ota discloses A method for increasing capacitors in a chip [0053] , comprising: determining a capacitance value needing to be increased in the chip ( [0054] : Ota discloses the need to adjust the capacitance of the emitter-base capacitor and provides for calculating the appropriate capacitance value based on device requirements ) ; according to the capacitance value, determining a length value of redundant metals required by a metal layer in the chip ([0054]: Ota discloses the lengths of lines opposed to each other in the comb-shaped portions (between capacitance adjustment lines 51 and 52 and between lines 53 and 52) can be adjusted to achieve the desired capacitance. The adjustment of the line lengths is directly based on the capacitance value, which maps to determining the required length of the redundant metals ); and inserting the redundant metals having a total length of the length value into a preset region of the metal layer ([0054]: Ota discloses the comb-shaped portions of the metal lines as predefined regions in which the redundant metals are formed. The disclosure shows that the adjusted lines are inserted into these predetermined regions of the device layout ) , and connecting the redundant metals to a power source ([0052]: 5, corresponding to powe r ) and a grounding power source ([0052]: 7, corresponding to ground ) ( The redundant metals are thus electrically connected to both a power source and a grounding source to function as capacitive elements ), wherein the redundant metals connected to the power source and the redundant metals connected to the grounding power source are arranged in an interdigital form (Fig 5, [0054]: the interdigitated arrangement of the redundant metals, where alternating fingers of the comb-shaped portions connect to the power (emitter) and ground (base) pads. This configuration corresponds directly to the claimed interdigital arrangement ) . Regarding claim 18. Ota discloses A chip, wherein redundant metals on the chip are connected to a power source and a grounding power source according to the method for increasing the capacitors in the chip according to claim 1, and are arranged in an interdigital form (Fig 5, [0052]) . Regarding claim 20. Ota discloses A semiconductor device, wherein the semiconductor device comprises the chip according to claim 18 (Fig 5) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2- 5 , 7-1 2 and 18- 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (US 20050269596 ) in view of Javanifard (US 6385033 ) . Regarding claim 2. Ota discloses The method for increasing the capacitors in the chip according to claim 1 . But Ota does not disclose wherein when there are a plurality of metal layers into which the redundant metals may be inserted, the redundant metals are inserted into the metal layer at a topmost layer of the plurality of metal layers. However, Fig 4 (top plan view) and Fig 6 (lateral view) of Javanifard wherein when there are a plurality of metal layers 212/312 (col 5, line 2-3) into which the redundant metals 334/334 may be inserted, the redundant metals are inserted into the metal layer at a topmost layer of the plurality of metal layers (Fig 6) . Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Ota’s device structure to have the Javanifard ’s structure for the purpose of providing enhanced cost reduction and eliminating extra masks fore fabrication. Thereby enhancing manufacturability. Regarding claim 3. Ota in view of Javanifard disclose The method for increasing the capacitors in the chip according to claim 2, Javanifard wherein the redundant metals are inserted into the metal layer at the topmost layer (Fig 6) , so as to reduce the number of through holes and to reduce transient voltage reduction ( Javanifard teaches that by inserting the capacitive redundant metals at the topmost layer (Fig. 6), the structure essential ly reduces the number of through-holes (vias) required to connect to the power source/package interface. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention t hat that minimizing the via stack directly reduces transient voltage reduction (IR drop) by lowering the parasitic resistance and inductance associated with vertical interconnects. Because Javanifard illustrates a direct connection at the top layer without redundant vertical through-holes, the combined teachings essentially possess the claimed functional properties. The recitation of "reducing transient voltage" is merely a statement of the essential electrical result of the structural arrangement taught by Javanifard ). Regarding claim 4. Ota discloses The method for increasing the capacitors in the chip according to claim 1 . But Ota does not explicitly recite wherein when there are a plurality of metal layers into which the redundant metals may be inserted, the redundant metals are inserted into the plurality of metal layers, and the redundant metals are sequentially inserted into the metal layers downwards from the metal layer at a topmost layer of the plurality of metal layers. But Javanifard , in a related field of power grid stabilization, teaches an integrated decoupling capacitor system utilizing a plurality of metal layers (212/312). Javanifard explicitly prioritizes the upper metal layers (Col. 5, lines 1-10) because global wiring layers possess lower resistance and inductance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ota’s method to follow a sequential downward insertion logic as taught by Javanifard for the purpose of electrically efficient layers (those with the lowest parasitic impedance) are utilized first. Furthermore, in modern multi-layer routing, global layers often provide the largest contiguous "preset regions" for fill, making a top-down sequential approach a matter of routine design optimization for maximizing decoupling efficiency. Regarding claim 5. Ota in view of Javanifard discloses The method for increasing the capacitors in the chip according to claim 4, wherein in the case that the redundant metals cannot be completely inserted into the metal layer at the topmost layer, the redundant metals are inserted into the plurality of metal layers, and the redundant metals are sequentially inserted into the metal layers downwards from the metal layer at the topmost layer ( Javanifard acknowledges that the available area in any given metal layer for capacitive fill is constrained by primary signal routing and density design rules. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention t hat in the event the topmost layer cannot completely accommodate the required redundant metal length (due to pre-existing routing congestion), the remaining required length must be allocated to the next available lower metal layer. This "overflow" logic represents a finite number of identified, predictable solutions to the problem of space constraints in semiconductor layout. The sequential "top-down" filling is the most predictable method for a designer to satisfy a total capacitance target while adhering to the layer-specific density constraints inherent in the CMP (Chemical Mechanical Polishing) processes discussed in Ota. Therefore, the conditional movement to lower layers as recited in Claim 5 is a result of routine engineering practice and lacks any unexpected technical effect beyond the sum of the combined teachings . Regarding claim 7. Ota discloses The method for increasing the capacitors in the chip according to claim 1, wherein determining the capacitance value needing to be increased in the chip comprises: determining the capacitance value according to a width value, a spacing and a thickness value of the metal layer ([0054]: Ota discloses determining capacitance based on the physical dimensions and arrangement of opposing metal lines ). But Ot does not disclose as well as a dielectric constant of a dielectric layer in the chip. However, Javanifard teaches that capacitance is a function of conductor geometry and dielectric properties (see col. 4, lines 20–45). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ota’s method to have the Javanifard ’s method for the purpose of providing enhanced decoupling efficiency. Therefore, determining capacitance based on width, spacing, thickness, and dielectric constant reflects well-known interconnect capacitance relationships, rendering claim 7 obvious. Regarding claim 8. Ota discloses The method for increasing the capacitors in the chip according to claim 1 . But Ota does not explicitly disclose wherein, according to the capacitance value, determining the length value of redundant metals required by the metal layer in the chip, comprises: determining a relative area of adjacent redundant metals according to a preset formula, wherein the preset formula is: C = ε r S /4 π kd in the formula, C denotes the capacitance value, ε r denotes a relative dielectric constant, d denotes a distance between the adjacent redundant metals, k denotes a static power constant, and S denotes the relative area of the adjacent redundant metals; and determining the length value according to the relative area and a thickness of the redundant metals. However, Ota discloses adjusting capacitance by changing the lengths of opposed metal lines [0054]. And Javanifard discloses calculating electrode area to achieve a target capacitance (col 2, line 65-67, col 3, line 1-7, col 6, line 28-36). Therefore, u sing a formula to relate capacitance to electrode area, spacing, and dielectric properties is a routine analytical technique in the art. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Ota in view of Javanifard ’s method discloses the claimed a routine analytical technique . Accordingly, claim 8 is unpatentable as an obvious mathematical implementation of known capacitance design principles. Furthermore, i t was well known in semiconductor design that capacitance relates to conductor geometry, dielectric properties, and surface area. A skilled artisan would have been motivated to apply such known capacitance relationships to determine a relative conductor area S that corresponds to a target capacitance and, from that relative area, determine a required conductor length L (e.g., area = length × thickness) as recited in claim 8. Regarding claim 9. Ota in view of Javanifard discloses The method for increasing the capacitors in the chip according to claim 8, wherein a formula for determining the length value is: S = L×d in the formula, S denotes the relative area of the adjacent redundant metals, d denotes the thickness of the redundant metals, and L denotes the length value of the redundant metals (N either Ota nor Javanifard teaches the specific formula. Nonetheless, applying the basic geometric relationship between area and dimension (area = length × thickness) to the redundant metal features of Ota — especially given the emphasis on interdigitated finger structures in Javanifard — would have been a routine design approach recognizable to a skilled artisan. The interdigitated finger capacitance in Javanifard (adjacent fingers separated by dielectric) reinforces that dimension relationships between length and area directly affect capacitance ) . Regarding claim 10. Ota discloses The method for increasing the capacitors in the chip according to claim 1, wherein when inserted into the metal layer, the redundant metals having the total length of the length value are divided into a plurality of segments of the redundant metals (Fig 5, [0052]-[0054]: Ota discloses forming redundant metal structures in a metal layer to adjust capacitance, wherein the redundant metals are implemented as comb-shaped portions comprising multiple discrete metal fingers connected to a power source and a grounding power source. These comb-shaped portions inherently divide the redundant metals into multiple segments . But Ota does not explicitly d isclose a part of divided redundant metals is connected to the power source, and the other part of the divided redundant metals is connected to the grounding power source. However, Javanifard discloses dividing capacitor electrodes into a plurality of finger segments, with different sets of segments connected to different terminals (see col. 6, lines 10–35; Figs. 5–7). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to divide the redundant metals of Ota into multiple segments and connect portions to power and ground, as taught by Javanifard , in order to provide controllable capacitance using known interdigitated capacitor structures. Regarding claim 11. Ota in view of Javanifard discloses The method for increasing the capacitors in the chip according to claim 10, wherein the part of the divided redundant metals connected to the power source and the other part of the divided redundant metals connected to the grounding power source are distributed alternately ( Ota explicitly discloses that the comb-shaped metal fingers are arranged such that adjacent fingers are connected to different nodes, thereby forming an interdigitated arrangement (see Fig. 5 , [0054]). Further, Javanifard likewise teaches alternating finger electrodes connected to opposite terminals. Accordingly, the alternating distribution recited in claim 11 is expressly taught or, at minimum, strongly suggested by Ota in view of Javanifard ) . Regarding claim 12. Ota in view of Javanifard discloses The method for increasing the capacitors in the chip according to claim 10, wherein the part of the divided redundant metals connected to the power source and the other part of the divided redundant metals connected to the grounding power source are distributed in parallel ( Javanifard teaches arranging multiple capacitor fingers in parallel configurations within a metal layer or across layers to increase effective capacitance (see col. 5, lines 45–65). It would have been obvious to arrange the segmented redundant metals of Ota in parallel as a known alternative capacitor layout yielding predictable capacitance behavior ) . Claim s 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (US 20050269596 ). Regarding claim 6. Ota discloses The method for increasing the capacitors in the chip according to claim 1, wherein when there are a plurality of metal layers into which the redundant metals may be inserted, the metal layer into which the redundant metals are inserted is a layer with a minimum density of metal wires ( Ota discloses inserting redundant metals into a metal layer to adjust capacitance [0052] –[ 0054]. While Ota does not expressly rank metal layers by density, it is well known in semiconductor layout practice to preferentially insert additional metal features into layers or regions having lower metal density in order to satisfy density balance, CMP uniformity, and routing constraints. Therefore, i t would have been obvious to one of ordinary skill in the art to select the metal layer with the minimum metal density for inserting Ota’s redundant metals, as this represents a routine optimization yielding predictable manufacturing and layout benefits ) . Regarding claim 19. Ota discloses The chip according to claim 18 . But Ota does not explicitly disclose wherein a substrate material of the chip is a composite material of silicon dioxide and aluminum nitride, or a composite material of silicon dioxide and silicon nitride, or silicon dioxide doped with high-valence cations. However, s uch substrate materials are well known in the semiconductor art for dielectric and thermal optimization. Selection of these known materials constitutes an obvious matter of design choice. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention t hat Ota’s substrate includes claimed type of substrate, e.g. SOI substate with composite material of silicon dioxide and silicon nitride for the purpose of providing higher thermal conductivity for better heat dissipation, increased mechanical strength, and superior chemical stability . Claims 13- 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (US 20050269596 ) in view of well-known electronic design automation (EDA)–based metal density analysis and layout optimization techniques routinely employed in integrated circuit physical design . Regarding claim 13. Ota discloses The method for increasing the capacitors in the chip according to claim 1 But Ota does not explicitly disclose wherein the determination process of the preset region comprises: determining an initial density of metal wires in each grid region in a layout corresponding to the chip; judging whether the initial density is lower than a preset lowest density threshold value; and if the initial density is lower than the preset lowest density threshold value, determining that the grid region corresponding to the initial density is the preset region. Although Ota does not explicitly disclose grid-based density determination, EDA-based metal density analysis is a fundamental and well-established practice in integrated circuit layout design. Standard physical-design workflows routinely divide layouts into grid or window regions, calculate local metal density for each region, and compare the calculated density against minimum density thresholds specified by fabrication process rules to ensure CMP uniformity, manufacturability, and interconnect reliability. It would have been obvious to one of ordinary skill in the art to apply this well-known density analysis when selecting regions for inserting Ota’s redundant metals, as such analysis is routinely used to identify low-density regions suitable for additional metal insertion. Regarding claim 14. Ota in view of EDA tools discloses The method for increasing the capacitors in the chip according to claim 13, wherein when the initial density is not lower than the preset lowest density threshold value and is lower than a preset highest density threshold value, the method comprises: determining a density difference between the grid region and an adjacent grid region; judging whether the density difference exceeds a preset difference threshold value; and if the density difference exceeds the preset difference threshold value, determining that the grid region is the preset region ( EDA tools commonly evaluate density gradients between adjacent grid regions to prevent abrupt metal density transitions that may adversely affect planarization and reliability. Applying this known density-difference evaluation to the selection of preset regions for redundant metal insertion would have been an obvious and routine design choice ) . Regarding claim 15. Ota in view of EDA tools discloses The method for increasing the capacitors in the chip according to claim 14, wherein when the density difference does not exceed the preset difference threshold value, the redundant metals are not filled in the grid region ( This limitation reflects the straightforward and predictable outcome of standard density-based decision logic employed in EDA metal fill processes and would have been obvious to one of ordinary skill in the art ) . Regarding claim 16. Ota in view of EDA tools The method for increasing the capacitors in the chip according to claim 14, wherein after the step of inserting the redundant metals having the total length of the length value into the preset region of the metal layer, and connecting the redundant metals to the power source and the grounding power source, the method further comprises: determining a density of the grid region after the redundant metals are inserted, using the density as a new initial density, and executing the step of judging whether the initial density is lower than the preset lowest density threshold value, until the density difference between the each grid region and the adjacent grid region does not exceed the preset difference threshold value ( Iterative density recalculation following metal insertion is a routine and well-known EDA practice, wherein density is recomputed after each insertion step and the process is repeated until density uniformity criteria are satisfied. Applying such iterative recalculation to Ota’s redundant metal insertion yields predictable results and would have been obvious ) . Regarding claim 17. Ota in view of EDA tools discloses The method for increasing the capacitors in the chip according to claim 13, wherein determining the initial density of metal wires in the each grid region in the layout corresponding to the chip comprises: dividing the layout into several grid regions by means of an EDA tool, and calculating the density of the metal wires in the each grid region ( The use of EDA tools to divide layouts into grids and calculate local metal density is notorious and conventional in semiconductor physical design. Therefore, claim 17 is unpatentable as an obvious implementation of known EDA techniques ) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Changhyun Yi whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7799 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday: 8A-4P . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Davienne Monbleau can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1945 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/ Primary Examiner, Art Unit 2812