CTNF 18/574,986 CTNF 90543 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on December 28, 2023. Information Disclosure Statement The information disclosure statement (IDS) submitted on December 28, 2023 is being considered by the examiner. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: Protection Circuit With ESD and avalanche robustness and Semiconductor Device . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-2, 4-5, 13, 18, and 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hutchings (US Pat. No. 5,352,915) . Claim 1 , Hutchings discloses (Figs. 3-4) a protection circuit comprising a first insulated gate field-effect transistor ( T1 , first insulated gate field effect device, Col. 4, lines: 40-60) in which: a first main electrode ( D , first main electrode, Col. 4, lines: 40-60) is coupled between an external terminal ( 21 , high voltage terminal, Col. 8, lines: 50-65) and an internal circuit ( T2 , IGFET, col. 8, lines: 30-40); a second main electrode ( S1 , source electrode, Col. 8, lines: 1-10) and a gate electrode ( G1 , gate, Col. 7, lines: 16-35) are coupled (both S1 and G1 are connected to ground Y ) to a reference power supply ( Y , ground, Col. 7, lines: 1-15); and an electric charge accumulation section (portion of 8 accumulates charge, Col. 5, lines: 1-35, hereinafter “ section ”) configured to accumulate hot carriers (hot carrier injection in section ) is provided in a gate insulating film ( 8 , gate oxide layer, Col. 6, lines: 6-15). Claim 2 , Hutchings discloses (Figs. 3-4) the protection circuit according to claim 1, further comprising a resistance ( 20b , resistive connection, Col. 5, lines: 1-20) that is electrically coupled in series between the gate electrode and the second main electrode ( 20b is electrically coupled in series with G1 and S1 ). Claim 4 , Hutchings discloses (Figs. 2-4) a semiconductor device comprising an external terminal ( 21 , high voltage terminal, Col. 8, lines: 50-65) provided on ( 21 would be on 2a ) a substrate ( 2a , silicon substrate, Col. 5, lines: 50-60), an internal circuit ( T2 , IGFET, col. 8, lines: 30-40) provided on the substrate ( T2 is on 2a ) and coupled to the external terminal ( T2 is coupled to 21 ), and a protection circuit (circuit comprising T1 , hereinafter “ circuit ”) provided on the substrate ( circuit is on 2a ) and including a first insulated gate field-effect transistor ( T1 , first insulated gate field effect device, Col. 4, lines: 40-60) in which: a first main electrode ( D , first main electrode, Col. 4, lines: 40-60) is coupled between the external terminal and the internal circuit ( D is coupled between 21 and T2 ); a second main electrode ( S1 , source electrode, Col. 8, lines: 1-10) and a gate electrode ( G1 , gate, Col. 7, lines: 16-35) are coupled (both S1 and G1 are connected to ground Y ) to a reference power supply ( Y , ground, Col. 7, lines: 1-15); and an electric charge accumulation section (portion of 8 accumulates charge, Col. 5, lines: 1-35, hereinafter “ section ”) configured to accumulate hot carriers (hot carrier injection in section ) is provided in a gate insulating film ( 8 , gate oxide layer, Col. 6, lines: 6-15). Claim 5 , Hutchings discloses (Figs. 2-4) the semiconductor device according to claim 4, wherein the protection circuit ( circuit ) further includes a resistance ( 20b , resistive connection, Col. 5, lines: 1-20) that is electrically coupled in series between the gate electrode and the second main electrode ( 20b is electrically coupled in series with G1 and S1 ). Claim 13 , Hutchings discloses (Figs. 2-4) the semiconductor device according to claim 4, wherein the first insulated gate field-effect transistor ( T1 ) causes hot carriers to be accumulated in the electric charge accumulation section and causes a threshold voltage to shift to a positive direction from a depletion type into an enhancement type (applying a voltage above a threshold voltage to insulated gate will cause inversion, Col. 6, lines: 16-25). Claim 18 , Hutchings discloses (Figs. 2-4) the semiconductor device according to claim 4, further comprising an inductive resistance ( L , inductive load, Col. 8, lines: 58-67) that is electrically coupled in series between the external terminal and the first main electrode ( L is coupled in series between 21 and D ). Claim 20 , Hutchings discloses (Figs. 2-4) the semiconductor device according to claim 4, wherein a plurality of the first insulated gate field-effect transistors is provided symmetrically (Fig. 2, shows a plurality of T1 which are symmetrical) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hutchings (US Pat. No. 5,352,915) as applied to claim 4 above, and further in view of Shukuri (US 2003/0198086) . Claim 7 , Hutchings discloses the semiconductor device according to claim 4. Hutchings does not explicitly discloses wherein the electric charge accumulation section is configured with a structure in which an oxide film, a nitride film, and an oxide film are stacked one by one. However, Shukuri discloses (Fig. 58) wherein an electric charge accumulation section ( 182/183/184 ) is configured with a structure in which an oxide film ( 182 , silicon oxide film, Para [0004]), a nitride film ( 183 , silicon nitride film, Para [0004]), and an oxide film ( 184 , silicon oxide film, Para [0004]) are stacked one by one ( 182-184 are stacked one by one). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the ONO structure of Shukuri to the section of Hutchings as it provides a system where retention characteristics are strong (Shukuri, Para [0004]). Claim 8 , Hutchings in view of Shukuri discloses the semiconductor device according to claim 7. Shukuri discloses (Fig. 58) wherein the nitride film ( 183 ) includes SiN ( 183 includes silicon nitride, Para [0004]), and the oxide film ( 182/184 ) includes at least one or more selected from Al 2 O 3 , HfO 2 , Ta 2 O 5 , ZrO 2 , Y 2 O 3 , and SiO 2 ( 182/184 are silicon oxide, Para [0004]). Claim 9 , Hutchings in view of Shukuri discloses the semiconductor device according to claim 7. Shukuri discloses (Fig. 58) wherein the electric charge accumulation section ( section of Hutchings) includes Al 2 O 3 , HfO 2 stacked on the Al 2 O 3 , SiN stacked on the HfO 2 , and SiO 2 stacked on the SiN ( 184 silicon oxide is stacked on 183 silicon nitride) . 07-22-aia AIA Claim (s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hutchings (US Pat. No. 5,352,915) as applied to claim 4 above, and further in view of Kobayashi (US 2018/0183392). Claim 10 , Hutchings discloses (Figs. 2-4) the semiconductor device according to claim 5. Hutchings does not explicitly disclose wherein the first insulated gate field-effect transistor includes a compound semiconductor. However, Kobayashi discloses (Fig. 10) a GaN transistor Q1 (Para [0049]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the compound semiconductor GaN material of Kobayashi to the transistor of Hutchings as they can form optimized power transistors (Kobayashi, Para [0004]) . Claim 11 , Hutchings in view of Kobayashi discloses the semiconductor device according to claim 10. Kobayashi discloses (Fig. 10) wherein the compound semiconductor includes GaN or GaAs ( Q1 is a GaN transistor). Claim 12 , Hutchings in view of Kobayashi discloses the semiconductor device according to claim 11. Kobayashi discloses (Fig. 10) wherein the first insulated gate field-effect transistor includes InAlN (channel region 64 of Q1 GaN transistor can be InAlN, Para [0049]) . 07-21-aia AIA Claim (s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hutchings (US Pat. No. 5,352,915) . Claim 15 , Hutchings discloses (Figs. 2-4) the semiconductor device according to claim 5. Hutchings does not explicitly disclose wherein the resistance is formed to be 100 Ω or more and 10 M Ω or less. However, Hutchings discloses that the resistance 20b may be 50 ohms or additional resistance (Col. 7, lines: 20-30). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable of resistance (result effective at least insofar as the resistance affects the current flow) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed resistance or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3, 6, 14-17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Hutchings (US Pat. No. 5,352,915), Shukuri (US 2003/0198086), Kobayashi (US 2018/0183392), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim: Regarding Claim 3 , a second external terminal coupled to the second main electrode and receiving supply of second power that generates hot carriers; and a third external terminal coupled to the gate electrode and receiving supply of third power that generates hot carriers. Regarding Claim 6 , a second external terminal coupled to the second main electrode and receiving supply of second power that generates hot carriers; and a third external terminal coupled to the gate electrode and receiving supply of third power that generates hot carriers. Regarding Claim 14 , wherein a gate length of the first insulated gate field-effect transistor in a direction coinciding with a direction in which the first main electrode and the second main electrode are disposed is formed to be 0.05 µm or more and 0.3 µm or less, and a gate width in a direction intersecting the direction of the gate length is formed to be 10 µm or more and 10000 µm or less. Regarding Claim 16 (from which claims 17 depends) , further comprising a power amplifier including a second insulated gate field-effect transistor formed as a depletion type. Regarding Claim 19 , further comprising a coupling capacitor that is electrically coupled in series between the external terminal and the internal circuit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUSTAVO G RAMALLO/Examiner, Art Unit 2812 Application/Control Number: 18/574,986 Page 2 Art Unit: 2812 Application/Control Number: 18/574,986 Page 3 Art Unit: 2812 Application/Control Number: 18/574,986 Page 4 Art Unit: 2812 Application/Control Number: 18/574,986 Page 5 Art Unit: 2812 Application/Control Number: 18/574,986 Page 6 Art Unit: 2812 Application/Control Number: 18/574,986 Page 7 Art Unit: 2812 Application/Control Number: 18/574,986 Page 8 Art Unit: 2812 Application/Control Number: 18/574,986 Page 9 Art Unit: 2812
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