DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of claims 1-6 in the reply filed on 04/16/26. Applicant’s election is acknowledged. Examiner notes, however, that given the application filed under §371, the restriction requirement dated 04/16/26 is withdrawn. Examiner will examine claims 1-7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe(USPGPUB DOCUMENT: 2019/0081171, hereinafter Watanabe) in view of Bu (USPGPUB DOCUMENT: 2019/0229211, hereinafter Bu).
Re claim 1 Watanabe discloses a silicon carbide[0003] semiconductor device comprising:a silicon carbide[0003] substrate of a first conductivity type[0078,0095]; a semiconductor layer formed on the silicon carbide[0003] substrate and containing silicon carbide[0003]; a first semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] formed on an upper portion in the semiconductor layer; a second semiconductor region(4/12/5/6/2/3/13/14/15) of a second conductivity type[0078,0095] different from the first conductivity type[0078,0095], the second semiconductor region(4/12/5/6/2/3/13/14/15) being formed in the semiconductor layer from a lower end of the first semiconductor region(4/12/5/6/2/3/13/14/15); a third semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] formed in the semiconductor layer under the second semiconductor region(4/12/5/6/2/3/13/14/15); a gate electrode(8) formed inside the insulating film(10/7);; a fourth semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] formed in the silicon carbide[0003] substrate; a fifth semiconductor region(4/12/5/6/2/3/13/14/15) of the second conductivity type[0078,0095] formed in the third semiconductor region(4/12/5/6/2/3/13/14/15) below the second semiconductor region(4/12/5/6/2/3/13/14/15); and a sixth semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] formed between the second semiconductor region(4/12/5/6/2/3/13/14/15) and the third semiconductor region(4/12/5/6/2/3/13/14/15) in the semiconductor layer, wherein the first semiconductor region(4/12/5/6/2/3/13/14/15), the gate electrode(8), the second semiconductor region(4/12/5/6/2/3/13/14/15), and the fourth semiconductor region(4/12/5/6/2/3/13/14/15) constitute a field effect transistor[0069], the first side surface is in contact with the second semiconductor region(4/12/5/6/2/3/13/14/15), the first side surface and the second side surface are alternately arranged in the first direction, the insulating film(10/7) includes a first insulating film(10/7) covering the first side surface, a second insulating film(10/7) covering the second side surface, and a third insulating film(10/7) covering a bottom surface of the trench, an impurity concentration[0060,0065,0072,0099] of the sixth semiconductor region(4/12/5/6/2/3/13/14/15) is higher than an impurity concentration[0060,0065,0072,0099] of the third semiconductor region(4/12/5/6/2/3/13/14/15) and lower than an impurity concentration[0060,0065,0072,0099] of the first semiconductor region(4/12/5/6/2/3/13/14/15),
Watanabe does not discloses the second semiconductor region(4/12/5/6/2/3/13/14/15) being formed in the semiconductor layer from a lower end of the first semiconductor region(4/12/5/6/2/3/13/14/15) to an intermediate depth of the semiconductor layer; a trench formed from the upper surface of the semiconductor layer to an intermediate depth of the third semiconductor region(4/12/5/6/2/3/13/14/15), the trench including a first side surface and a second side surface facing each other in a first direction along the upper surface of the semiconductor layer; and a plurality of the trenches and a plurality of the fifth semiconductor region(4/12/5/6/2/3/13/14/15)s in contact with the trenches are formed side by side in the first direction, a film thickness of the second insulating film(10/7) is larger than a film thickness of the first insulating film(10/7) in the first direction, the fifth semiconductor region(4/12/5/6/2/3/13/14/15) is in contact with a first surface extending over the first side surface of the trench and a part of the bottom surface, and is separated from a second surface extending over the second side surface of the trench and another part of the bottom surface, the sixth semiconductor region(4/12/5/6/2/3/13/14/15) is in contact with the first side surface and the second side surface of the trench and is separated from a third side surface of the trench in a second direction intersecting the first direction in plan view, and the fifth semiconductor region(4/12/5/6/2/3/13/14/15) covers all corners of four corners of the bottom surface of the trench.
Bu discloses a trench(11 of Bu) formed from the upper surface of the semiconductor layer
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Bu to the teachings of Watanabe in order to have the voltage withstanding property of the gate insulating film is improved and increase of the on-resistance caused by energization deterioration can be prevented [0011, Bu]. In doing so, a trench(11 of Bu) formed from the upper surface of the semiconductor layer to an intermediate depth of the third semiconductor region(4/12/5/6/2/3/13/14/15), the trench (11 of Bu) including a first side surface and a second side surface facing each other in a first direction along the upper surface of the semiconductor layer; and a plurality of the trenches and a plurality of the fifth semiconductor region(4/12/5/6/2/3/13/14/15)s in contact with the trenches(11 of Bu) are formed side by side in the first direction, , the fifth semiconductor region(4/12/5/6/2/3/13/14/15) is in contact with a first surface extending over the first side surface of the trench and a part of the bottom surface, and is separated from a second surface extending over the second side surface of the trench and another part of the bottom surface, the sixth semiconductor region(4/12/5/6/2/3/13/14/15) is in contact with the first side surface and the second side surface of the trench(11 of Bu) and is separated from a third side surface of the trench in a second direction intersecting the first direction in plan view, and the fifth semiconductor region(4/12/5/6/2/3/13/14/15) covers all corners of four corners of the bottom surface of the trench.
Watanabe and Bu does not discloses the second semiconductor region(4/12/5/6/2/3/13/14/15) being formed in the semiconductor layer from a lower end of the first semiconductor region(4/12/5/6/2/3/13/14/15) to an intermediate depth of the semiconductor layer; a film thickness of the second insulating film(10/7) is larger than a film thickness of the first insulating film(10/7) in the first direction
Although the combination of Watanabe and Bu does not discloses the second semiconductor region(4/12/5/6/2/3/13/14/15) being formed in the semiconductor layer from a lower end of the first semiconductor region(4/12/5/6/2/3/13/14/15) to an intermediate depth of the semiconductor layer; a film thickness of the second insulating film(10/7) is larger than a film thickness of the first insulating film(10/7) in the first direction, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose the second semiconductor region(4/12/5/6/2/3/13/14/15) being formed in the semiconductor layer from a lower end of the first semiconductor region(4/12/5/6/2/3/13/14/15) to an intermediate depth of the semiconductor layer; a film thickness of the second insulating film(10/7) is larger than a film thickness of the first insulating film(10/7) in the first direction as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize in order to have the voltage withstanding property of the gate insulating film is improved and increase of the on-resistance caused by energization deterioration can be prevented [0011, Bu]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 2 Watanabe and Bu disclose the silicon carbide[0003] semiconductor device according to claim 1, further comprising:a source electrode formed on the semiconductor layer and connected to the first semiconductor region(4/12/5/6/2/3/13/14/15); and a seventh semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] formed between the fifth semiconductor region(4/12/5/6/2/3/13/14/15)s adjacent to each other in the first direction, wherein each of the fifth semiconductor region(4/12/5/6/2/3/13/14/15) and the seventh semiconductor region(4/12/5/6/2/3/13/14/15) extends in the second direction, and a plurality of the source electrodes extend in the first direction and is arranged side by side in the second direction.
Re claim 3 Watanabe and Bu disclose the silicon carbide[0003] semiconductor device according to claim 1, wherein the gate electrode(8) has a first portion extending in the second direction on the semiconductor layer and a second portion formed inside each of the plurality of trenches, andthe plurality of second portions of the gate electrode(8) are connected in parallel by the first portion of the gate electrode(8).
Re claim 4 Watanabe and Bu disclose the silicon carbide[0003] semiconductor device according to claim 3, wherein the first portion of the gate electrode(8) is connected to each of the plurality of second portions of the gate electrode(8) immediately above an end of the trench in the second direction.
Re claim 5 Watanabe and Bu disclose the silicon carbide[0003] semiconductor device according to claim 1, wherein in the second direction, a shortest distance from the third side surface to a terminal end of the fifth semiconductor region(4/12/5/6/2/3/13/14/15) in contact with the trench is equal to or longer than a distance between the third side surface and the gate electrode(8).
Re claim 6 Watanabe and Bu disclose the silicon carbide[0003] semiconductor device according to claim 1, further comprising an eighth semiconductor region(4/12/5/6/2/3/13/14/15) of the second conductivity type[0078,0095] formed in contact with the second side surface in an upper portion in the semiconductor layer, wherein the eighth semiconductor region(4/12/5/6/2/3/13/14/15) is electrically connected to the second semiconductor region(4/12/5/6/2/3/13/14/15).
Re claim 7 Watanabe discloses a method of manufacturing a silicon carbide[0003] semiconductor device, the method comprising:(a) preparing a semiconductor substrate including a silicon carbide[0003] substrate of a first conductivity type[0078,0095] and a semiconductor layer of the first conductivity type[0078,0095] formed on the silicon carbide[0003] substrate, containing silicon carbide[0003], and having a third semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095Re claim Watanabe and Bu disclose therein; (b) forming a first semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] on an upper surface of the semiconductor layer, forming a second semiconductor region(4/12/5/6/2/3/13/14/15) of a second conductivity type[0078,0095] different from the first conductivity type[0078,0095] in the semiconductor layer from a lower end of the first semiconductor region(4/12/5/6/2/3/13/14/15) to an intermediate depth of the semiconductor layer, forming a sixth semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] in the semiconductor layer from the lower end of the second semiconductor region(4/12/5/6/2/3/13/14/15) to the intermediate depth of the semiconductor layer, and forming a plurality of fifth semiconductor region(4/12/5/6/2/3/13/14/15)s of the second conductivity type[0078,0095] in the third semiconductor region(4/12/5/6/2/3/13/14/15) below the second semiconductor region(4/12/5/6/2/3/13/14/15);(c) (f) forming a gate electrode(8) made of the conductive film by removing a portion of the conductive film facing the second side surface; and (g) embedding a second insulating film(10/7) in a region (f), wherein the silicon carbide[0003] substrate includes a fourth semiconductor region(4/12/5/6/2/3/13/14/15) of the first conductivity type[0078,0095] inside, the first semiconductor region(4/12/5/6/2/3/13/14/15), the gate electrode(8), the second semiconductor region(4/12/5/6/2/3/13/14/15), and the fourth semiconductor region(4/12/5/6/2/3/13/14/15) constitute a field effect transistor[0069], the first side surface is in contact with the second semiconductor region(4/12/5/6/2/3/13/14/15), a plurality of the fifth semiconductor region(4/12/5/6/2/3/13/14/15)s, the first side surface and the second side surface are alternately arranged in the first direction, , an impurity concentration of the sixth semiconductor region(4/12/5/6/2/3/13/14/15) is higher than an impurity concentration of the third semiconductor region(4/12/5/6/2/3/13/14/15) and lower than an impurity concentration of the first semiconductor region(4/12/5/6/2/3/13/14/15), the gate electrode(8) has a first portion extending in the second direction the plurality of second portions of the gate electrode(8) are connected in parallel by the first portion of the gate electrode(8),
Watanabe does not discloses forming a plurality of trenches including a first side surface and a second side surface facing each other in a first direction along the upper surface of the semiconductor layer from the upper surface of the semiconductor layer to an intermediate depth of the third semiconductor region(4/12/5/6/2/3/13/14/15); (d) forming a first insulating film(10/7) covering a side surface and a bottom surface of the trench; (e) forming a conductive film inside the trench and on the upper surface of the semiconductor layer via the first insulating film(10/7);(g) embedding a second insulating film(10/7) in a region in the trench from which the conductive film has been removed in and a plurality of the trenches and a plurality of the fifth semiconductor region(4/12/5/6/2/3/13/14/15)s in contact with the trenches are formed side by side in the first direction, the fifth semiconductor region(4/12/5/6/2/3/13/14/15) is in contact with a first surface extending over the first side surface of the trench and a part of the bottom surface, and is separated from a second surface extending over the second side surface of the trench and another part of the bottom surface, the gate electrode(8) has a first portion extending in the second direction and a second portion formed inside each of the plurality of trenches on the semiconductor layer, and the first portion of the gate electrode(8) is connected to each of the plurality of second portions of the gate electrode(8) immediately above an end of the trench in the second direction.
Bu discloses a trench(11 of Bu)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Bu to the teachings of Watanabe in order to have the voltage withstanding property of the gate insulating film is improved and increase of the on-resistance caused by energization deterioration can be prevented [0011, Bu]. In doing so, forming a plurality of trench(11 of Bu)es including a first side surface and a second side surface facing each other in a first direction along the upper surface of the semiconductor layer from the upper surface of the semiconductor layer to an intermediate depth of the third semiconductor region(4/12/5/6/2/3/13/14/15); (d) forming a first insulating film(10/7) covering a side surface and a bottom surface of the trench(11 of Bu); (e) forming a conductive film inside the trench(11 of Bu) and on the upper surface of the semiconductor layer via the first insulating film(10/7);(g) embedding a second insulating film(10/7) in a region in the trench(11 of Bu) from which the conductive film has been removed in and a plurality of the trench(11 of Bu)es and a plurality of the fifth semiconductor region(4/12/5/6/2/3/13/14/15)s in contact with the trench(11 of Bu)es are formed side by side in the first direction, the fifth semiconductor region(4/12/5/6/2/3/13/14/15) is in contact with a first surface extending over the first side surface of the trench(11 of Bu) and a part of the bottom surface, and is separated from a second surface extending over the second side surface of the trench(11 of Bu) and another part of the bottom surface, the gate electrode(8) has a first portion extending in the second direction and a second portion formed inside each of the plurality of trench(11 of Bu)es on the semiconductor layer, and the first portion of the gate electrode(8) is connected to each of the plurality of second portions of the gate electrode(8) immediately above an end of the trench(11 of Bu) in the second direction.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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