DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claims 1-20 are objected to because of the following informalities: Claim 1 recites “ the pixel” (line 4) which should be replaced with “ a pixel”, to avoid antecedent basis issue. Claim 1 recites “ the adjacent pixels” (line 5) which should be replaced with “adjacent pixels”, to avoid antecedent basis issue. Claim 1 recites “ the outside” (line 7) which should be replaced with “outside”, to avoid antecedent basis issue. Claim 1 recites “ the charges” (line 12) which should be replaced with “charges”, to avoid antecedent basis issue. Claim 6 recites “a pair of the feedback enable transistors” which should be replaced with “a pair of feedback enable transistors”, to avoid antecedent basis issue. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1 -3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura et al. (hereinafter Nishimura) in view of Webster (US 2021/0029311) and Ren (CN 101815179 A) . With respect to claim 1, Nishimura discloses a solid-state imaging apparatus (e.g., imaging device 100 , see the annotated Fig. 9K below ) (Nishimura, Figs. 4-5, 9K, ¶0345-¶0354, ¶0363, ¶0374, ¶038 0 -¶0389) including a pixel array unit (1) (Nishimura, Figs. 4-5, 9K, ¶0345-¶0346) in which a plurality of pixels are arranged in an array, wherein each of the plurality of pixels (e.g., 1a/1a’) includes: a photoelectric converter (PC1/PC2) (Nishimura, Figs. 5, 9K, ¶0351, ¶0353 , ¶0380-¶0383 ) that generates an amount of charge corresponding to light incident from the outside; 209550 980440 0 0 a plurality of transistors (e.g., M10-M13, M20-M23) (Nishimura, Fig. 9K, ¶0352, ¶0354, ¶0376, ¶0380-¶0382) , including a transistor (M12/M22) formed at one end of the photoelectric converter (PC1/PC2) ; a floating diffusion region ( e.g., read-out node FD) (Nishimura, Fig. 9K, ¶0352, ¶0376, ¶0380-¶0382) formed to temporarily store the charges generated and transferred by the photoelectric converter (PC1/PC2) ; the plurality of transistors further includes: a reset transistor (M12 /M22 ) (Nishimura, Fig. 9K, ¶0374, ¶0380-¶0382) for resetting a potential of the floating diffusion region (FD1) ; and a feedback enable transistor (M13 /M23 , perfor ming band control of the fee d back circuit FBAMP1/FBAMP2 ) connected to a feedback amplifier circuit (FBAMP1 /FBAMP2 ) for canceling out voltage noise of the reset transistor (M12 /M22 ) . Further, Nishimura does not specifically disclose (1) a pixel separator that defines an outer edge shape of the pixel and is formed between the adjacent pixels; a floating diffusion region formed around the photoelectric converter; and a shielding portion formed around the photoelectric converter to block light leaking from the photoelectric converter and directed toward the floating diffusion region; and the shielding portion includes a first shielding portion that blocks light directed toward a portion of the floating diffusion region formed near the feedback enable transistor; (2) a transfer transistor formed at one end of the photoelectric converter to transfer the charge generated by the photoelectric converte r . Regarding (1), Webster teaches forming a pixel separator (e.g., outer deep trench isolation (DTI) structure 388A/388B or the outer DTI ring 488 , see the annotated Fig. 3 below ) (Webster, Figs. 2-5, ¶00 45 -¶00 46, ¶0051-¶0052 ) that defines an outer edge shape of the pixel and is formed between the adjacent pixels; a floating diffusion region (e.g., FD 250A/250B, FD 350A/350B, 4FD 50A/450B) (Webster, Figs. 2-5, ¶0027-¶0028, ¶0037, ¶0051) formed around (e.g., at the right and left sides of the photoelectric converter (e.g., photodiode 232 or 302); and a shielding portion (e.g., 380A/380B or the inner DTI ring 480) formed around the photoelectric converter (e.g., photodiode 232 or 302) (Webster, Figs. 2-5, ¶0027-¶0028, ¶0041, ¶0053) to 276225 152400 0 0 block light leaking from the photoelectric converter and directed toward the floating diffusion region ( e.g., FD 250A/250B, FD 350A/350B, 4 FD 50A/450B) (Webster, Figs. 2-5, ¶0027-¶0028, ¶0037, ¶0051) ; and the shielding portion (e.g., 380A/380B or the inner DTI ring 480) includes a first shielding portion (e.g., the inner DTI ring 480) that blocks light directed toward a portion of the floating diffusion region (e.g., FD 450A) formed near the shatter transistor (444A/242A). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura by forming the inner and outer deep trench isolation (DTI) structures around the photoelectric converter as taught by Webster, wherein the feedback enable transistor of Nishimura is formed to contact the floating diffusion region formed between the outer DTI ring and the inner DT I ring to have the solid-state imaging apparatus , wherein each of the plurality of pixels includes: a pixel separator that defines an outer edge shape of the pixel and is formed between the adjacent pixels; a floating diffusion region formed around the photoelectric converter; and a shielding portion formed around the photoelectric converter to block light leaking from the photoelectric converter and directed toward the floating diffusion region; and the shielding portion includes a first shielding portion that blocks light directed toward a portion of the floating diffusion region formed near the feedback enable transistor, in order to isolate the readout circuits from the light collection region, and to prevent interference or cross talk between the readout circuits of adjacent pixels (Webster, ¶0027-¶0028, ¶0046, ¶0053). 523875 2272030 0 0 Regarding (2), Ren teaches forming 5T type (five transistors) CMOS image sensor (see the annotated Fig. 6 below) (Ren, Figs. 5-6, ¶0003, ¶0037-¶0039, ¶0073-¶0099) comprising a transfer transistor (M4) (Ren, Figs. 5-6, ¶0074, ¶0087) formed at one end of the photoelectric converter (PD) to transfer the charge generated by the photoelectric converter (PD) to the floating diffusion (FD) connected to the reset transistor (M1) that is connected to feedback amplifier circuit (203) to stabilize potential of the sensing node (FD), and to eliminate the reset transistor noise . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura by forming a transfer transistor at one end of the photoelectric converter and the sensing node connected to the resent transistor and the feedback amplifier circuit as taught by Ren to have the solid-state imaging apparatus , wherein each of the plurality of pixels includes: a transfer transistor formed at one end of the photoelectric converter to transfer the charge generated by the photoelectric converter, in order to provide 5T CMOS image sensor with stabilized potential of the sensing node, and eliminated reset transistor noise (Ren, ¶0003, ¶0037-¶0039, ¶0074, ¶0087, ¶0099). Regarding claim 2, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the shielding portion is formed to reflect light leaking from the photoelectric converter toward the photoelectric converter. However, Webster teaches that the shielding portion (e.g., the inner DTI ring 3 80) (Nishimura, Figs. 2-5, ¶0045-¶0046) surrounding the photoelectric converter (232/302) is formed of dielectric material or metal material to improve total internal reflection. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by forming the inner and outer deep trench isolation (DTI) structures comprised of specific material as taught by Webster to have the solid-state imaging apparatus , wherein the shielding portion is formed to reflect light leaking from the photoelectric converter toward the photoelectric converter , in order to improve total internal reflection, and to isolate the readout circuits from the light collection region, and to prevent interference or cross talk between the readout circuits of adjacent pixels (Webster, ¶0027-¶0028, ¶0045-¶0046, ¶0053). Regarding claim 3, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the shielding portion has a bent portion formed along an outer peripheral edge of the photoelectric converter. However, Webster teaches that the shielding portion (e.g., the inner DTI ring 480) (Nishimura, Figs. 2-5, ¶0045-¶0046 , ¶0052-¶0053 ) surrounding the photoelectric converter (232/302) has a horizontal portion and the vertical portion such that a bent portion formed along an outer peripheral edge of the photoelectric converter (232/302) to improve total internal reflection. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by forming the inner and outer deep trench isolation (DTI) structures surrounding the photoelectric converter and having horizontal portions and vertical portions as taught by Webster to have the solid-state imaging apparatus , wherein the shielding portion has a bent portion formed along an outer peripheral edge of the photoelectric converter , in order to improve total internal reflection, and to isolate the readout circuits from the light collection region, and to prevent interference or cross talk between the readout circuits of adjacent pixels (Webster, ¶0027-¶0028, ¶0045-¶0046, ¶0053). Claim s 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311) and Ren (CN 101815179) as applied to claim 1, and further in view of Hynecek (US 2014/0085523). Regarding claim 4, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the portion of the floating diffusion region formed near the feedback enable transistor is formed on a distal side of the feedback enable transistor with respect to the photoelectric converter . However, Hynecek teaches a pixel circuit layout comprising t he floating diffusion region (604) ( Hynecek , Figs. 2, 4, 6, ¶0027-¶0028, ¶0037-¶0046) near the feedback enable transistor (e.g., reset transistor 408 connected to the feedback amplifier 412), wherein the portion of the floating diffusion region (604) formed near the feedback enable transistor (e.g., the gate 606 of the reset transistor connected to the feedback amplifier) is formed on a distal side of the feedback enable transistor (606) with respect to the transfer gate (600) that transferring charges from the storage well (the photoelectric converter ), to mitigate noise in the pixel . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by configuring a pixel circuit layout as taught by Hynecek to have the solid-state imaging apparatus , wherein t he portion of the floating diffusion region formed near the feedback enable transistor is formed on a distal side of the feedback enable transistor with respect to the photoelectric converter , in order to reduce pixel area, and to mitigate noise in the pixel ( Hynecek , ¶0028, ¶0042, ¶0046). Regarding claim 12, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the plurality of transistors further includes at least one charge drain transistor formed at the other end of the photoelectric converter different from the one end to drain charges remaining in the photoelectric converter . However, Hynecek teaches a pixel circuit layout comprising charge drain gate (60 2 ) ( Hynecek , Figs. 2, 4, 6, ¶002 6 -¶0028, ¶0037-¶0046) formed a t the other end (e.g., left side of the charge storage well 202, as in Fig. 2) of the photoelectric converter different from the one end (e.g., right side of the charge storage well 202) ( Hynecek , Figs. 2, 4, 6, ¶0026 , ¶0044 ) to drain charges remaining in the photoelectric converter (e.g., charge storage well 202) , to remove overflow charges into the drain diffusion region (206) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by configuring a pixel comprising overflow charge drain gate as taught by Hynecek to have the solid-state imaging apparatus , wherein t he plurality of transistors further includes at least one charge drain transistor formed at the other end of the photoelectric converter different from the one end to drain charges remaining in the photoelectric converter , in order t o remove overflow charges into the drain diffusion region ( Hynecek , ¶002 6 , ¶004 4 , ¶0046). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311), Ren (CN 101815179), and Hynecek (US 2014/0085523) as applied to claim 4, and further in view of Hamasaki (US Patent No. 5,274,459) and Zang et al. (US 2021/0118925, hereinafter Zang). Regarding claim 5, Nishimura in view of Webster, Ren, and Hynecek discloses the solid-state imaging apparatus according to claim 4. Further, Nishimura does not specifically disclose that the feedback enable transistor is configured as a vertical transistor made of polycrystalline silicon. However, Hamasaki teaches forming image sensing device (Hamasaki, Figs. 2-3, Col. 3, lines 39-65; Col. 4, lines 55-66) comprising a feedback transistor (4) including a polysilicon gate (26) and connected to the vertical selection transistor (5), to increase the sensitivity and to reduce the smear. Further, Zang teaches forming a pixel cell (200B) (Zang, Fig. 2B, ¶0002, ¶0015, ¶0037-¶0039) with vertical gate structures including transfer gate, reset gate, source follower gate, and select gate which are formed in vertical tranches in a semiconductor substrate and filled with appropriate gate material and having a shape, to provide improved cell having high resolution, improved isolation, low power consumption, and low random noise. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/ Hynesec by forming a feedback transistor including a polysilicon gate as taught by Hamasaki , wherein a pixel includes vertical gate structures as taught by Zang to have the solid-state imaging apparatus , wherein t he feedback enable transistor is configured as a vertical transistor made of polycrystalline silicon , in order to increase the sensitivity and to reduce the smear ; and to provide improved cell having high resolution, improved isolation, low power consumption, and low random noise (Hamasaki, Col. 1, lines 44-48; Col. 4, lines 55-66 ; Zang, ¶0002, ¶0015, ¶0037 ). Claim s 6 -7 , 9-10 , 15-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311) and Ren (CN 101815179) as applied to claim 1, and further in view of Katayama et al. (WO 2020/008907, US 2021/0255282 is presented as translation, hereinafter Katayama). Regarding claim 6 , Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the portion of the floating diffusion region formed near the feedback enable transistor is formed between a pair of the feedback enable transistors. However, Katayama teaches a light receiving element (Katayama, Fig. 15, ¶0010, ¶0094-¶0104, ¶0188-¶0191) including a pixel having configuration to reduce signal degradation during charge transfer, and improve conversion efficiency, wherein the floating diffusion regions (FD1-FD4) and pluralities of transistors surround the photodiode region (PD) at four sides, such that the portion of the floating diffusion region (e.g., FD2 at the upper side of the PD) formed near the reset transistor (RST2) is formed between a pair of reset transistors (RST1 and RST3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by forming the floating diffusion regions and the pluralities of transistors surrounding the photodiode region as taught by Katayama, wherein each of the pluralities of transistors includes a feedback enable transistor on each side of the photodiode region to have the solid-state imaging apparatus , wherein the portion of the floating diffusion region formed near the feedback enable transistor is formed between a pair of the feedback enable transistors , in order to provide improved a pixel with reduced signal degradation during charge transfer and improved conversion efficiency ( Katayama , ¶0010, ¶0071-¶0076, ¶0188-¶0191 ). Regarding claims 7 and 9, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the plurality of transistors further includes a switching transistor formed around the photoelectric converter to electrically couple the floating diffusion region to an additional capacitance, and the shielding portion further includes a second shielding portion that blocks light directed toward another portion of the floating diffusion region formed near the switching transistor (as claimed in claim 7); wherein the switching transistor is configured as a vertical transistor made of polycrystalline silicon (as claimed in claim 9) . However, Katayama teaches a light receiving element (Katayama, Fig. 15, ¶0010, ¶0074, ¶0094-¶0104, ¶0188-¶0191) including a pixel having configuration to reduce signal degradation during charge transfer, and improve conversion efficiency, wherein the floating diffusion regions (FD1-FD4) and pluralities of transistors surround the photodiode region (PD) at four sides, and the pluralities of transistors comprise a switching transistor (e.g., FDG1-FDG4) formed around the photoelectric converter (e.g., photodiode PD) to electrically couple (e.g., the source of the switching transistor FDG1 is used as a floating diffusion region FD1) the floating diffusion region (FD1) to an additional capacitance (FDL1) (Katayama, Fig. 15, ¶0074, ¶0094), wherein the transfer transistor s (Katayama, Fig. 15, ¶0108, ¶0113, ¶0117-¶0125) are configured as a vertical transistor made of polycrystalline silicon (polysilicon), to reduce the transfer time of charges . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren b y forming the floating diffusion regions and the pluralities of transistors surrounding the photodiode region and including a switching transistor as taught by Katayama, wherein the switching transistor is configured as a vertical transistor to have the solid-state imaging apparatus , wherein the plurality of transistors further includes a switching transistor formed around the photoelectric converter to electrically couple the floating diffusion region to an additional capacitance (as claimed in claim 7); wherein the switching transistor is configured as a vertical transistor made of polycrystalline silicon (as claimed in claim 9), in order to provide improved a pixel with reduced signal degradation during charge transfer and improved conversion efficiency (Katayama, ¶0010, ¶0071-¶0076, ¶0188-¶0191). Further, Webster teaches forming the shielding portion (e.g., DTI 480) (Nishimura, Figs. 2-5, ¶0045-¶0046, ¶0052-¶0053) includ ing horizontal portions and vertical portions to block light directed toward the floating diffusion region and the plurality of transistor s formed between the outer DTI ring and the inner DTI ring. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/Katayama by forming the inner and outer deep trench isolation (DTI) structures surrounding the photoelectric converter and having horizontal portions and vertical portions as taught by Webster , wherein the plurality of transistors including a switching transistor is formed between the inner and outer deep trench isolation (DTI) structures to have the solid-state imaging apparatus , wherein the shielding portion further includes a second shielding portion that blocks light directed toward another portion of the floating diffusion region formed near the switching transistor (as claimed in claim 7) , in order to improve total internal reflection, and to isolate the readout circuits from the light collection region, and to prevent interference or cross talk between the readout circuits of adjacent pixels (Webster, ¶0027-¶0028, ¶0045-¶0046, ¶0053). Regarding claim 10, Nishimura in view of Webster, Ren, and Katayama discloses the solid-state imaging apparatus according to claim 7. Further, Nishimura does not specifically disclose that t he other portion of the floating diffusion region formed near the switching transistor is formed to face between a pair of switching transistors . However, Katayama teaches a light receiving element (Katayama, Fig. 15, ¶0010, ¶0094-¶0104, ¶0188-¶0191) including a pixel having configuration to reduce signal degradation during charge transfer, and improve conversion efficiency, wherein the floating diffusion regions (FD1-FD4) and pluralities of transistors surround the photodiode region (PD) at four sides, such that the other portion of the floating diffusion region (e.g., FD4 at the lower side of the PD) formed near the reset transistor (FDG4) is formed between a pair of reset transistors (FDG1 and FDG3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/Katayama by forming the floating diffusion regions and the pluralities of transistors surrounding the photodiode region as taught by Katayama, wherein each of the pluralities of transistors includes a switching transistor on each side of the photodiode region to have the solid-state imaging apparatus , wherein t he other portion of the floating diffusion region formed near the switching transistor is formed to face between a pair of switching transistors , in order to provide improved a pixel with reduced signal degradation during charge transfer and improved conversion efficiency (Katayama, ¶0010, ¶0071-¶0076, ¶0188-¶0191). Regarding claims 15 -16 and 1 9 , Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the transfer transistor is configured as a vertical transistor made of polycrystalline silicon (as claimed in claim 15); wherein a vertical structure of the transfer transistor partially has a gap in a surface in a depth direction of the pixel (as claimed in claim 16) ; wherein the transfer transistor is configured as a pair of transistors for distributing the charges generated by the photoelectric converter to a pair of the floating diffusion regions at a predetermined timing, respectively (as claimed in claim 19) . However, Katayama teaches forming the transfer transistor s (Katayama, Fig. 15, ¶0108-¶0125) configured as a vertical transistor made of polycrystalline silicon (polysilicon) (Katayama, Fig. 15, ¶0113) , to reduce the transfer time of charges, wherein a vertical structure of the transfer transistor partially has a gap (e.g., a space between vertical gate electrode portions 42V 2 ) i n a surface in a depth direction of the pixel. Further, with the vertical transfer gate (TRG) (Katayama, Figs. 4, 15, ¶0114-¶0116) on both sides of the photoelectric converter (e.g., photodiode 41), the floating diffusion regions (43 1 and 43 2 ) are formed on opposite sides of the photoelectric converter (41), wherein the first transfer transistor TRG1 and t he second transfer transistor TRG 2 are turn on at different timing (Katayama, Figs. 4, 15, ¶0192-¶0196). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by forming the transfer gate transistor s as taught by Katayama to have the solid-state imaging apparatus , wherein the transfer transistor is configured as a vertical transistor made of polycrystalline silicon (as claimed in claim 15); wherein a vertical structure of the transfer transistor partially has a gap in a surface in a depth direction of the pixel (as claimed in claim 16 ) ; wherein the transfer transistor is configured as a pair of transistors for distributing the charges generated by the photoelectric converter to a pair of the floating diffusion regions at a predetermined timing, respectively (as claimed in claim 19), in order to provide improved a pixel with reduced signal degradation during charge transfer and improved conversion efficiency (Katayama, ¶0010, ¶0071-¶0076, ¶0188-¶0191). Claim s 8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311), Ren (CN 101815179), and Katayama (WO 2020/008907) as applied to claim 7, and further in view of Choi et al. (US 2021/0025993, hereinafter Choi). Regarding claim 8, Nishimura in view of Webster, Ren, and Katayama discloses the solid-state imaging apparatus according to claim 7. Further, Nishimura does not specifically disclose that the switching transistor is formed to have a bent portion . However, Choi teaches forming a pixel circuit (Choi, Fig. 3, ¶0019, ¶0049-¶0053) including a switching transistor and a floating diffusion region (FD1/FD2) having a portion at the channel region (350A/350B) (Choi, Fig. 3, ¶0049-¶0053) formed between the switching transistor (338A 338B) and shutter transistor (340A/340B), to facilitate charge transfer to floating diffusion regions (346A/346B (Choi, Fig. 3, ¶0052), wherein t he switching transistor is formed to have a bent portion near the charge storage portion (344A/344B) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/Katayama by forming the floating diffusion regions and the switching transistor s as taught by Choi to have the solid-state imaging apparatus , wherein t he switching transistor is formed to have a bent portion , in order to provide switching transistor s to facilitate charge transfer to floating diffusion regions, and to obtain improved image sensor having low power consumption and improved charge transfer speed (Choi, ¶0019, ¶0049-¶0053). Regarding claim 10, Nishimura in view of Webster, Ren, and Katayama discloses the solid-state imaging apparatus according to claim 7. Further, Nishimura does not specifically disclose that t he other portion of the floating diffusion region formed near the switching transistor is formed to face between a pair of switching transistors . However, Choi teaches forming a pixel circuit (Choi, Fig. 3, ¶0019, ¶0049-¶0053) including a switching transistor and a floating diffusion region (FD1/FD2) having a portion at the channel region (350A/350B) (Choi, Fig. 3, ¶0049-¶0053) formed between the switching transistor (338A 338B) and shutter transistor (340A/340B), such that a portion of the floating diffusion region (e.g., FD1/FD2 at the channel region 350A/350B) formed near the switching transistor is formed to face between a pair of switching transistors (SW1/SW2). The switching transistors (338A/338B) are formed to facilitate charge transfer to floating diffusion regions (346A/346B (Choi, Fig. 3, ¶0052). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/Katayama by forming the floating diffusion regions and the switching transistor s as taught by Choi to have the solid-state imaging apparatus , wherein t he other portion of the floating diffusion region formed near the switching transistor is formed to face between a pair of switching transistors , in order to facilitate charge transfer to floating diffusion regions, and to provide improved image sensor having low power consumption and improved charge transfer speed ( Choi , ¶001 9 , ¶00 49 -¶00 53 ). Regarding claim 11, Nishimura in view of Webster, Ren, and Katayama discloses the solid-state imaging apparatus according to claim 7. Further, Nishimura does not specifically disclo se that the other portion of the floating diffusion region formed near the switching transistor is formed on a distal side of the switching transistor with respect to the photoelectric converter . However, Choi teaches forming a pixel circuit including a switching transistor and a floating diffusion region (FD1/FD2) having a portion at the end of the channel region (350A/350B) formed between the switching transistor (338A 338B) and shutter transistor (340A/340B), such that the portion of the floating diffusion region (e.g., FD1/FD2 at the end of the channel region 350A/350B) formed near the switching transistor is formed on a distal side of the switching transistor (338A 338B) with respect to the photoelectric converter (PD 332) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/Katayama by forming the floating diffusion regions and the switching transistor s as taught by Choi to have the solid-state imaging apparatus , wherein t he other portion of the floating diffusion region formed near the switching transistor is formed on a distal side of the switching transistor with respect to the photoelectric converter , in order to facilitate charge transfer to floating diffusion regions, and to provide improved image sensor having low power consumption and improved charge transfer speed (Choi, ¶0019, ¶0049-¶0053). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311), Ren (CN 101815179), and Katayama (WO 2020/008907) as applied to claim 7, and further in view of Miyake et al. (US Patent No. 5.525,813, hereinafter Miyake). Regarding claim 8, Nishimura in view of Webster, Ren, and Katayama discloses the solid-state imaging apparatus according to claim 7. Further, Nishimura does not specifically disclose that the switching transistor is formed to have a bent portion . However, Miyake teaches forming an image sensor (Miyake, Fig. 5, Col. 3, lines 48-56; Col. 8, lines 35-59) including a photoelectric conversion element (38) and transistors including gate electrodes (21a/21b) formed around the photoelectric conversion element (38), such that each transistor is formed to have a bent portion , to reduce the size of the image sensor element. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/Katayama by forming transistors including gate electrodes around the photoelectric conversion element as taught by Miyake, wherein the transistors include a switching element to have the solid-state imaging apparatus , wherein t he switching transistor is formed to have a bent portion , in order to reduce the size of the image sensor element (Miyake, Col. 3, lines 48-56; Col. 8, lines 35-59). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311), Ren (CN 101815179), and Katayama (WO 2020/008907) as applied to claim 7, and further in view of Zang (US 2021/0118925). Regarding claim 9, Nishimura in view of Webster, Ren, and Katayama discloses the solid-state imaging apparatus according to claim 7. Further, Nishimura does not specifically disclo se that the switching transistor is configured as a vertical transistor made of polycrystalline silicon. However, Zang teaches forming a pixel cell (200B) (Zang, Fig. 2B, ¶0002, ¶0015, ¶0037-¶0039) with vertical gate structures including transfer gate, reset gate, source follower gate, and select gate which are formed in vertical tranches in a semiconductor substrate and filled with appropriate gate material and having a shape, to provide improved cell having high resolution, improved isolation, low power consumption, and low random noise. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren/Katayama by forming a pixel cell with vertical gate structures as taught by Zang, wherein the gate structures include a switching transistor to have the solid-state imaging apparatus , wherein the switching transistor is configured as a vertical transistor made of polycrystalline silicon , in order to provide improved cell having high resolution, improved isolation, low power consumption, and low random noise (Zang, ¶0002, ¶0015, ¶0037). Claim s 12 -14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311) and Ren (CN 101815179) as applied to claim 1, and further in view of Azami et al. (US 2016/0351606, hereinafter Azami). Regarding claim 12, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the plurality of transistors further includes at least one charge drain transistor formed at the other end of the photoelectric converter different from the one end to drain charges remaining in the photoelectric converter (as claimed in claim 12); wherein the charge drain transistor is configured as a vertical transistor made of polycrystalline silicon (as claimed in claim 13); wherein a vertical structure of the charge drain transistor partially has a gap in a surface in a depth direction of the pixel (as claimed in claim 14) . However, Azami teaches forming imaging device comprising discharge transistor ( 29 ) (Azami, Figs. 1, 9, 14, ¶0035, ¶0024, ¶0099-¶0101 , ¶0119-¶0121 ) formed a t the other end (e.g., including overflow drain 37 at opposite side of the charge ac c umulation/memory region 35 from the floating diffusion region 36 , as in Fig. 14 ) of the photoelectric converter different from the one end (e.g., at the floating diffusion 36), wherein t he discharge transistor ( 29 ) functions as an overflow gate that allows the charge to flow from the PD to the overflow drain (37); wherein the charge drain transistor is configured as a vertical transistor (e.g., having vertical gate electrode 41C) ; and wherein a vertical structure (41C) of the charge drain transistor partially has a gap (e.g., a space between the end of the vertical gate 41C above a surface of the substrate) (Azami, Fig. 9) in a surface in a depth direction of the pixel . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by forming a discharge transistor as taught by Azami, wherein the discharge transistor includes a vertical gate electrode made of polysilicon to have the solid-state imaging apparatus , wherein t he plurality of transistors further includes at least one charge drain transistor formed at the other end of the photoelectric converter different from the one end to drain charges remaining in the photoelectric converter (as claimed in claim 12); wherein the charge drain transistor is configured as a vertical transistor made of polycrystalline silicon (as claimed in claim 13); wherein a vertical structure of the charge drain transistor partially has a gap in a surface in a depth direction of the pixel (as claimed in claim 14) , in order to effectively remove overflow charges into the overflow drain , and to reduce the pixel size ( Azami , ¶00 01 , ¶0013, ¶0048, ¶0 101 , ¶0 121 ). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311) and Ren (CN 101815179) as applied to claim 1, and further in view of Lenchenkov et al. (US 2015/0060966, hereinafter Lenchenkov ). Regarding claim 17, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that the shielding portion is a dummy transistor having a semiconductor stacked structure made of polycrystalline silicon . However, Lenchenkov teaches forming an imaging device ( Lenchenkov , Figs. 1, 5, ¶0007, ¶0020-¶0021, ¶0038-¶0044, ¶0052) comprising shielding structures formed as dummy gate structures (400/402) that are not a part of the active transistor s and comprised of poly silicon and silicide as a silicide light shield, to efficiently block light. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by forming s hielding structures as dummy gate structures as taught by Lenchenkov to have the solid-state imaging apparatus , wherein the shielding portion is a dummy transistor having a semiconductor stacked structure made of polycrystalline silicon , in order to efficiently block light, and to provide image sensor with improved inter-pixel shielding arrangements ( Lenchenkov , ¶000 7 , ¶0020-¶0021, ¶0039, ¶0041, ¶0043-¶0044 ). Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311) and Ren (CN 101815179) as applied to claim 1, and further in view of Takahashi et al. (US 2021/0074747, hereinafter Takahashi). Regarding claim 18, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose that a well contact for electrically connecting to a semiconductor conductive region of the pixel is formed near the floating diffusion region . However, Takahashi teaches forming an image sensor (Takahashi, Figs. 1-6, 8 , ¶0021-¶0033 ) with improved interconnect structure including conductive vias (130) (Takahashi, Figs. 1-6, 8, ¶0023-¶0026, ¶0029) electrically coupled well contact regions (114a-1 1 4b) formed near the floating diffusion regions (116a-b) and transistors (e.g., readout transistors 120a-120c) to one another, which are arranged to reduce a total conductive density of the interconnect stricture to improve noise performance (Takahashi, Figs. 1-6, 8, ¶0033) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by forming interconnect structure including conductive vias coupled to the well contact regions and the transistors as taught by Takahashi to have the solid-state imaging apparatus , wherein a well contact for electrically connecting to a semiconductor conductive region of the pixel is formed near the floating diffusion region , in order to provide an image sensor including improved interconnect structure with reduced total conductive density of the interconnect stricture to improve noise performance (Takahashi, ¶0001, ¶0023-¶0026, ¶0041, ¶0033). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0105424 to Nishimura in view of Webster (US 2021/0029311) and Ren (CN 101815179) as applied to claim 1, and further in view of Yasu et al. (US 2019/0074315 , hereinafter Yasu ). Regarding claim 20, Nishimura in view of Webster and Ren discloses the solid-state imaging apparatus according to claim 1 . Further, Nishimura does not specifically disclose a distance image sensor device for acquiring a distance image based on distance information to an object obtained by the solid-state imaging apparatus according to claim 1 . However, Yasu teaches forming a distance image sensor ( Yasu , Figs. 1, 27, ¶00 04 -¶00 06, ¶0042-¶0049, ¶0180-¶0185 ) comprising a sensor chip including a pixel array unit with a plurality of sensor elements arranged in an array pattern to improve speed performance and acquire more accurate distance image ( Yasu , ¶0 185 ). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modif y the solid-state imaging apparatus of Nishimura/Webster/ Ren by f orming a distance image sensor including an image sensor as taught by Yasu to have a distance image sensor device for acquiring a distance image based on distance information to an object obtained by the solid-state imaging apparatus according to claim 1 , in order to provide a distance image sensor with improved speed performance and accurate distance image (Yasu, ¶0004-¶0006, ¶0049, ¶0185 ). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NATALIA GONDARENKO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-2284 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9:30 AM-7:30 PM . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891