DETAILED ACTION
This application, 18/4575382, attorney docket Q292519, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Samsung Electronics Co., Ltd., and claims foreign priority to 10-2023-0090554, filed 07/12/2023. Claims 1-12 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Response to Arguments
Applicant has amended claims 1 and 11 to define two dielectric layers and correctly argues that the amendment overcomes rejection based on the art of record because Nakayama has only one insulation layer (INSL), therefore, the rejection is withdrawn and a new rejection is presented below.
Examiner notes that the art teaches an electron supply layer, which is known in the art as a barrier layer. See Shimizu U.S. 2021/0118984, [0236].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4 - 6 rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 recites, “the second insulating film is outside the first insulation film” it is not clear how the applicant defines “outside”. The term is a relative term which renders the claim indefinite. The term “outside” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim 5 includes the same defect as its parent.
Claim 6 recites “the second insulating film includes a portion of the first insulating film.” This is undefined because the layers are claimed as different, and one “outside” the other, so one cannot include a portion of the other.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, and 7-11 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Okamoto et al. (U.S. 2015/0076511).
As for Claim 1,
Okamoto teaches in figure 1, a semiconductor device comprising an insulated-gate field-effect transistor, the insulated-gate field-effect transistor including:
a channel layer (13);
a pair of main electrodes (21,22) spaced from each other and are on the channel layer;
a barrier layer (14) on the channel layer wherein the barrier layer is between the pair of main electrodes and includes a recessed region (41) that goes through the barrier layer in a thickness direction;
a gate insulating film (32/31) on the channel layer in the recessed region,
wherein the gate insulation film includes a first insulation film (32) with a first thickness and includes a second insulating film (31) with a second thickness higher than the first thickness (at edges, the thickness includes more than the thickness of the horizontal portion of 32); and wherein the second insulation film is on the barrier layer and on the pair of main electrodes (at the sides)
a gate electrode (23) on the channel layer wherein the gate insulating film is between the gate electrode and the channel layer
As for Claim 2,
Okamoto teaches the semiconductor device according to claim 1, and teaches that a distance between the first insulation film and an end of the recessed region is greater than the first thickness of the first insulating (the distance to the bottom of the recess is the sum of the thickness of 32 and the depth to the channel region.)
As for Claim 3,
Okamoto teaches the semiconductor device according to claim 2, wherein the distance between the first insulation film and the end of the recessed region is equal to or more than 25 nm. (the thickness of the GE to the bottom is 10-15nm [0023], and the from the figure, the bottom of the gat’s shelf is more than three thickness: the thickness in recess plus the portion over the barrier plus at least one thickness between because a vertical wall can be seen, so the height to the shelf must be more than 30nm, and the distance to the edge must be greater than 30nm.).
As for Claim 4,
Okamoto teaches the semiconductor device according to claim 2, wherein the second insulating film is outside the first insulation film (shown in figure 1, where the where the vertical portion of 31 is not covered).
As for Claim 5,
Okamoto teaches the semiconductor device according to claim 4, and teaches that the first insulation film includes a first material different from a second material included in the second insulation film. (al3O3 and SiN, [0009,0010])
As for Claim 7,
Okamoto teaches the semiconductor device according to claim 1, and teaches that the gate insulating film includes multiple materials stacked in layers (31/32).
As for Claim 8,
Okamoto teaches the semiconductor device according to claim 1, and teaches that that the gate electrode extends from the recessed region to the barrier layer (The gate is formed in the recess, and extends through the barrier vertically and horizontally)
As for Claim 9,
Okamoto teaches the semiconductor device according to claim 1, and teaches that a position of a first interface between the channel layer and the gate insulating film coincides with a second position of a second interface between the channel layer and the barrier layer. All three share a point above the bottom of the recess along the sidewall of the gate insulation 32).
As for Claim 10,
Okamoto teaches the semiconductor device according to claim 2, and teaches that the first insulating film is in contact with a portion of the barrier layer (at the sidewalls of the recess) .
As for claim 11,
Okamoto teaches a semiconductor module, comprising a semiconductor device that includes an insulated-gate field-effect transistor, wherein the insulated-gate field-effect transistor includes
a channel layer (13);
a pair of main electrodes (21/22) spaced from each other and on the channel layer;
a barrier layer (14) channel layer, wherein the barrier layer is between the pair of main electrodes (extends from 21-22) and includes a recessed region (41) that goes through the barrier layer in a thickness direction;
a gate insulating film (32/31) on the channel layer in the recessed region,
wherein the gate insulating film includes a first insulating film (32) with a first thickness and includes a second insulating film (31) with a second thickness higher than the first thickness, and
wherein the second insulating film is on the barrier layer and on the pair of main electrodes;
and a gate electrode (23) on the channel layer, wherein the gate insulating film is between the gate electrode and the channel layer (both layers are between the gate and channel at the shelf portion of the gate).
Claim 12 is rejected under 35 U.S.C. 102a1/a2 as being anticipated by Oka et al. (U.S. 2014/0291775).
As for claim 12,
Oka teaches in figure 12, electronic apparatus, comprising; a semiconductor device that includes an insulated-gate field-effect transistor, wherein the insulated-gate field-effect transistor includes:
a channel layer (530)
a pair of main electrodes (610/620) spaced from each other and are on the channel layer (formed above the channel layer directly on the barrier layer);
a barrier layer (540) on the channel layer,
wherein the barrier layer is between the pair of main electrodes (extends from 610-620) and includes a recessed region (560) that goes through the barrier layer in a thickness direction;
a gate insulating film (590) on the channel layer in the recessed region,
wherein the gate insulating film includes a first insulating film (592) with a first thickness and includes a second insulating film (594) with a second thickness higher than the first thickness (thicknesses taught in figure 3 [0046]), and
wherein the second insulating film is on the barrier layer and on the pair of main electrodes; and
a gate electrode (630) on the channel layer, wherein the gate insulating film is between the gate electrode and the channel layer (shown in figure 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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