Prosecution Insights
Last updated: August 06, 2026
Application No. 18/575,477

METHODS OF FABRICATING A MULTIANALYTE DETECTION DEVICE AND DEVICES THEREOF

Non-Final OA §103§112
Filed
Dec 29, 2023
Priority
Jun 29, 2021 — provisional 63/216,039 +2 more
Examiner
PHAM, THOMAS T
Art Unit
1713
Tech Center
1700 — Chemical & Materials Engineering
Assignee
The Trustees of Boston College
OA Round
1 (Non-Final)
52%
Grant Probability
Moderate
1-2
OA Rounds
7m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 52% of resolved cases
52%
Career Allowance Rate
299 granted / 578 resolved
-13.3% vs TC avg
Strong +16% interview lift
Without
With
+15.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
42 currently pending
Career history
644
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
15.5%
-24.5% vs TC avg
§112
31.3%
-8.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 578 resolved cases

Office Action

§103 §112
DETAILED ACTION This is the Office action based on the 18575477 application filed December 29, 2023, and in response to applicant’s argument/remark filed on April 15, 2026. Claims 1-26 are currently pending and have been considered below. Applicant’s withdrawal of claims 16-26 acknowledged. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Applicant’s election, without traverse, of the invention of Group I, claims 1-15 in the reply filed on April 15, 2026 is acknowledged. Claims 16-26 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 recites “etching the graphene layer to remove the first portions of the graphene layer, wherein the second portions of the graphene layer form a plurality of graphene active regions between the source and the drain electrode of each of the plurality of graphene field effect transistors for detection of an analyte therein”, but the terms “the source and the drain electrode” lack antecedent basis. Although claim 1 recites “transferring a graphene layer onto a substrate having sources, drains, and side gates for a plurality of graphene field effect transistor devices located thereon” prior to the above sentence, the terms sources and drains are not equivalent to the terms “the source and the drain electrode”. One of skills in the art would not be clear how to etch the graphene layer to produce the plurality of graphene active regions between the source and the drain electrode without knowing the position of the source and the drain electrode. For the purpose of examining it will be assumed that the source and the drain electrode are the same as the source and the drain. Claim 3 rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. The terms “the deposited metal” lacks antecedent basis because no deposition of metal is recited previously. Claims 2-15 rejected under 35 U.S.C. 112(b) because they are directly or indirectly dependent on claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-12 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (“Detection of a multi-disease biomarker in Saliva with Graphene Field Effect Transistors”, Medical Devices & Sensors, Vol. 3, Issue 6, December 2020), hereinafter “Kumar”, in view of Hoffman et al. (U.S. PGPub. No. 20170018626), hereinafter “Hoffman”.--Claims 1, 2, 4, 7, 9, 10, 11, 12: Kumar teaches a method of manufacturing a G-FET device for biosensing, comprising (Section 2.1)i) obtaining a graphene layer that is formed over a SiO2/Si substrate, then baking the graphene layer at 300°C for 9 hr in vacuum to remove impurities and improving its adhesion to a substrate;ii) depositing a first protection layer of aluminum oxide on the graphene layer, then baking at 175°C for 5 min in Ar atmosphere to remove impurities and improving its adhesion of the aluminum oxide layer;iii) depositing a photoresist pattern on the graphene layer by lithography, then forming an electrode layer by depositing Au/Cr then lift-off by using a remover;iv) patterning the graphene layer by using photolithography and oxygen plasma ashing;v) depositing a second protection layer of aluminum oxide on the substrate, then baking at 175°C for 10 min;vi) forming an opening in the second protection layer by forming a photoresist mask, i.e. S1805 photoresist, then etching through the mask, wherein the opening comprises the biosensing window (Fig. (a) and Fig. (b) in page 6). It is noted that the photoresist pattern in step (iii) reads on the second photoresist, the photoresist mask in step (vi) reads on the third photoresist layer, the first protection layer reads on the first passivation layer, and the second protection layer reads on the second passivation layer, as recited in claim 1. Kumar fails to teach the claimed feature “transferring a graphene layer onto a substrate having sources, drains, and side gates for a plurality of graphene field effect transistor devices located thereon”. Hoffman, also directed to fabricating a G-FET for biosensing (abstract), teaches that the G-FET may be fabricated by using conventional CMOS chip fabrication to enable a large scale, high quality, low-cost manufacturing ([0014, 0018]), comprising providing a SiO2/Si substrate that includes a source electrode and a drain electrode in the SiO2 layer, then attaching a graphene layer (Fig. 17, [0309]) that provides a reaction zone to the substrate ([0066], Fig. 1 and 5A), then forming a protection layer on the graphene layer (Fig. 26D) then forming trenches through a protection layer to expose the source electrode and the drain electrode, then filling the trenches with copper or aluminum to form interconnection (Fig. 26E, 26I, [0329]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to use the a SiO2/Si substrate that includes a source electrode and a drain electrode as the substrate, then forming the interconnection to the electrode layer, i.e. step iii, in the invention of Kumar because Hoffman teaches that this would advantageously enable large scale, high quality, and low-cost manufacturing.--Claim 5: Since Kumar teaches that the first protection layer of aluminum oxide, having thickness 3 nm, and second protection layer of aluminum oxide, having thickness 20 nm, (Page 5) are to protect the graphene layer during manufacturing, the thickness of the aluminum oxide is a result-effective variable, and it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to optimize the thickness, such as to 50 nm or more, because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A). It is noted that Hoffman discloses that aluminum oxide passivation layer may have a suitable thickness, such as less than 9 nm to about 100 nm ([0035, 0212]).--Claims 6, 8: Hoffman teaches that the channel of the G-FET may have a length as short as a fabrication process may allow, such as of less than 20 nm -1 micron, and the width of the channel may be as wide as possible ([0198, 0331]). Therefore, the dimensions of the substrate and the window are result-effective variables, and it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to optimize the dimensions of the substrate and the window, such as to the claimed ranges, because it’s been well established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A). --Claim 15: Kumar further teaches to mount a PDMS well on the G-FET device (Section 2.1) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS PHAM whose telephone number is (571) 270-7670 and fax number is (571) 270-8670. The examiner can normally be reached on MTWThF9to6 PST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached on (571) 270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS T PHAM/Primary Examiner, Art Unit 1713
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Prosecution Timeline

Dec 29, 2023
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
52%
Grant Probability
68%
With Interview (+15.8%)
3y 2m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 578 resolved cases by this examiner. Grant probability derived from career allowance rate.

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