DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in this office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 , 5-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable Yumi et al DE102016204020A1 in view of Bruso et al US20140181368A1
Yumi discloses a method performed by an electronic control unit ECU, that includes a flash memory:
Page2 [p2] “According to one aspect of the present invention, an electronic control unit comprises: an electrically rewritable nonvolatile memory having a plurality of data storage areas each storing a plurality of data items having different write execution conditions with respect to the nonvolatile memory and a number storage area storing a maximum number of nonvolatile memory write operations”;
the method comprising
receiving a request to download and install a software update package:
page 8 [p4] “ If the microcomputer 3 , as in 3 shown, the write control processing starts, determines the microcomputer 3 first in S110, whether a write request for any of the data items related to the flash memory 11 is present. In the microcomputer 3 is the write request information (such as a flag)generated for each ID and”;
incrementing an update counter for an allocated software update memory of the flash memory with the update counter value to obtain an incremented update counter:
page 7 p[8] “ Subsequently, the microcomputer reads 3 in S140, the number of writes corresponding to the ID of the data item that is in S120 in the flash memory 11 is written from the number of writes for each ID in RAM 9 is stored, and the microcomputer increments 3 the read number of writes. The result of calculating the increment is stored in an internal register of the microcomputer 3 saved.
determining if the incremented update counter exceeds an update blocking value:
page 8 p[8] “Subsequently, the microcomputer determines 3 in the following S200, whether the maximum number of writes updated in S190 is an upper limit on the maximum number of times of writing the flash memory 11 exceeds”.
updating the ECU by downloading and installing the software update package in the allocated software update memory of the flash memory, in response to determining that the incremented update counter does not exceed the update blocking value:
page 8 p[9-11]” If the microcomputer 3 in S200 determines that the updated maximum number of writes does not exceed the limit for the number of writes, the microcomputer proceeds 3 ahead to S210.
….
The occurrence of the termination processing corresponds to the satisfaction of the completion processing execution condition, in this example, turning off the ignition switch. When it is determined in S210 that the termination processing has occurred, a write request for a data item whose storage time is "termination processing" (a data item whose ID is "0") is output before the start of the current write control processing. Consequently, in S120, the data item whose ID is "0" is written in the flash memory 11 written.
But not explicitly:
Determining a package size of the software update package and an update counter value based on the package size;
Bruso discloses:
Determining a package size of the software update package and an update counter value based on the package size;
[0074]”Two file blocks 1302, 1304 and a portion of file block 1306 may be updated in corresponding storage block 1312 in a single write request. The combined write request may include a combination of write requests for blocks 1302 and 1304, such as illustrated in FIG. 11, and a partial update of file block 1306, such as illustrated in FIG. 12. By tracking partial block updates as well as complete block updates, the file system may combine the updates into a single write request to the storage device”;
Bruso also discloses:
Increment the write count for the block/memory:
[0012]“The processor is configured to write data to a file block in a file system. The processor is also configured to increment a write counter associated with the file block.”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bruso into teachings of Yumi to aggregate concurrent partial writes of several blocks into to single write to single block. Thus, the improved process for storing data in solid state devices can be achieved. Reducing write operations performed on a storage device may be particularly advantageous for SSDs, because an entire storage block of an SSD is written with each write request to prevent uneven wear of an SSD .
As per claim 2, the rejection o claim 1 is incorporated and furthermore Yumi does not discloses:
wherein the update counter value is determined from a look-up-table, wherein the look-up-table provides a plurality of package size ranges, and wherein each of the package size ranges is associated with a corresponding one of a plurality of update counter values.
Bruso discloses:
wherein the update counter value is determined from a look-up-table, wherein the look-up-table provides a plurality of package size ranges, and wherein each of the package size ranges is associated with a corresponding one of a plurality of update counter values.
[0005]“At the left, a directory 102 links together a name for the file and the corresponding inode structure 104, which manages the contents of the file. The inode 104 points to blocks 106a-n, 108, and 112 on a storage device. The blocks may hold data or links to other index structures. The file system creates only the number of blocks required to hold the file contents. The direct blocks 106a-n, 108, and 112, indirect blocks 110a-n, 114a-n, and doubly indirect blocks 116a-n identify the areas on the storage device that hold the file data. When the size of a file block differs from the size of a storage block, the file system may maintain more control information about the relationship between a file block and its corresponding storage block or blocks”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bruso into teachings of Yumi to aggregate concurrent partial writes of several blocks into to single write to single block. Thus, the improved process for storing data in solid state devices can be achieved. Reducing write operations performed on a storage device may be particularly advantageous for SSDs, because an entire storage block of an SSD is written with each write request to prevent uneven wear of an SSD .
As per claim 5, the rejection of claim 1 is incorporated and furthermore Yumi discloses:
generating a warning signal is generated, if in response to determining that the incremented update counter exceeds the update blocking value:
page 8 p[4] “ Examples of the abnormality notification processing include processing for displaying a message indicating that the flash memory 11 the end of its life has reached an on-display in the vehicle as well as a processing to turn on a warning light, which indicates that the flash memory 11 has reached the end of his life. However, it is possible to use a different processing. Such an abnormality notification processing enables the user of the vehicle to recognize that a component (ie, the ECU 1 ) of the vehicle needs to be repaired or replaced”;
As per claim 6, the rejection of claim 1 is incorporated and furthermore Yumi discloses:
wherein the update counter is also increased and/or the update blocking value is decreased by the update counter value, if the updating of the ECU fails.
Page 9 [5]” S140, the microcomputer increments 3 the number of writes of the data item that in S120 into the flash memory 11 is written (ie, the number of writes corresponding to the ID of the written data item).”
Claim 9 is the an electronic control unit claim corresponding to method claim 1 and rejected under the same rational set forth in connection with the rejection of claim 1 above.
As per claim 10, the rejection of claim 1 is incorporated and furthermore Yumi discloses:
vehicle with an electronic control unit, ECU, according to claim 9.
Page 3[5] “An electronic control unit (hereinafter referred to as ECU) 1 the first embodiment, in the 1 for example, an ECU that controls an internal combustion engine of a vehicle is shown. The ECU 1 has a micro-computer 3 as a processing unit that controls the operation of the ECU 1 controls, and a power-supply circuit 4 on”;
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable Yumi et al DE102016204020A1 in view of Bruso et al US20140181368A1 and Guan et al US20110296082A1.
As per claim 3, the rejection of claim 1 is incorporated and furthermore Yumi does not discloses:
wherein the update blocking value is calculated by a writing budget of the allocated software update memory divided by a maximum value of a smallest one of the plurality of package size ranges.
Guan discloses:
[0050]” if the original bit data Bi is mapped as n-bit data in the flash, it results in only performing the block erasing once when directly writing n times, and the upper limit of n can be selected according to the practical requirements and the actual condition of the chip. The relationship between the number n of bits and the service life of flash (suppose the original life service of the flash is 100,000 times) is as shown in Table 3. Discloses”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Guan into teachings of Yumi and Bruso to reduce the time of erasing the flash block and improve the service life of the flash to a large extent. Therefore, the limitation to the flash in programming aspect is avoided, the speed of updating the data in the flash is accelerated, the times of erasing the flash block can be greatly reduced, and the service life of flash is improved to a large extent. [Guan 0018].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable Yumi et al DE102016204020A1 in view of Bruso et al US20140181368A1 and Bar-or et al US20160188464A1.
As per claim 4, the rejection of claim 2 is incorporated and furthermore Yumi does not discloses:
wherein the corresponding one of the plurality of update counter values for each of the plurality of package size ranges is calculated by a respective maximum value of each of the plurality of package size ranges divided through by a maximum value of a smallest one of the plurality of package size range ranges.
Bar-or discloses
wherein the corresponding one of the plurality of update counter values for each of the plurality of package size ranges is calculated by a respective maximum value of each of the plurality of package size ranges divided through by a maximum value of a smallest one of the plurality of package size ranges:
[0026]“For example, if the first non-volatile memory 104 has a tolerance for a certain amount of rewrites, a data size and an expected number of rewrites relative to the tolerance of the first non-volatile memory 104 and the first non-volatile memory 104 capacity, may be used to derive a criterion for differentiating between “friendly” data that can be stored in the first non-volatile memory 104 and ordinary DRAM data. In particular, if the capacity of the first non-volatile memory 104 is c, and its tolerance to rewrites is t, then a lifetime capacity of c.Math.t may be associated with the first non-volatile memory 104. A data of size s which is expected to be written a times may be associated with a lifetime capacity of a.Math.s. A threshold p can be set such that whenever a.Math.s>p.Math.c.Math.t, (i.e., whenever the lifetime capacity of a data chunk is larger than a given percentage of the lifetime capacity of the first non-volatile memory 104), the data will be assigned to ordinary DRAM 116 and not considered suitable for storage in the first non-volatile memory 104.”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bar-or into teachings of Yumi and Bruso to to determine the optimal mix of “fast DRAM” (the first non-volatile memory 104) and “slow DRAM” (the volatile memory 116) in the production version of the product. During the design phase, the product beta version may be equipped with a large amount of “fast DRAM” and “slow DRAM,” and the optimal mix of the two may be determined according to the statistics gathered through the process. [Bar-or 0046].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable Yumi et al DE102016204020A1 in view of Bruso et al US20140181368A1 and Ogle et al US20040088473A1.
As per claim 7, the rejection of claim 1 is incorporated and furthermore Yumi discloses:
determining a difference between a present ECU software version and an updated ECU software version, , wherein the software update package contains a delta update with the difference between the present ECU software version and the updated ECU software version.
Ogle discloses:
determining a difference between a present ECU software version and an updated ECU software version, wherein the software update package contains a delta update with the difference between the present ECU software version and the updated ECU software version.
[0013]” Accordingly, yet a further object of the invention is a space efficient storage of an update package expressing the difference between an original binary image and an updated version of that image. These small update packages may feasibly be transmitted over low-speed communications links (e.g. a GSM network), and stored on devices with limited available memory (e.g. a mobile phone).”
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Ogle into teachings of Yumi and Bruso to generate small update packages and y feasibly be transmitted over low-speed communications links (e.g. a GSM network), and stored on devices with limited available memory (e.g. a mobile phone)[Ogle 0013].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable Yumi et al DE102016204020A1 in view of Bruso et al US20140181368A1 and Vouchair et al US20150261458A1.
As per claim 8, the rejection of claim 1 is incorporated and furthermore, Yumi does not disclose:
wherein the ECU includes a protected testing routine, and wherein the update blocking value is disabled or manually set in the protected testing routine.
Vouchair discloses:
wherein the ECU includes a protected testing routine, and wherein the update blocking value is disabled or manually set in the protected testing routine:
[0072]”The test data value may be provided to the write engine 124 and also stored in one of the registers 138. The controller 110 then uses the write engine 124 to attempt 184 to write the test data value into the memory location that is being tested.”;
[0064]“In some embodiments, the controller 110 performs a first sequence of the write operations to repeatedly write the data value to a selected memory element or block. The first sequence of the write operations includes a number of write operations equal to or greater than a first threshold number of write cycles. The controller 110 then performs a second sequence of the write operations to write the data value to the selected memory element in response to a determination that the selected memory element can store a newly written data value”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Vouchair into teachings of Yumi and Bruso to allow a memory device to use wear leveling techniques to distribute the write operations across different blocks or segments of the memory element in order to avoid wearing out the blocks or segments of memory that is faster, so that the reprogrammable memory device cannot be easily investigated or read, thus preventing a subsequent write operation from changing the stored data value, and hence preventing wear leveling procedures for OTP memory elements and the repetitive write operations to drive the OTP memory elements to the write failure state quickly[Vouchair 0046]..
Pertinent arts:
US20150154110A1:
[0024] “. When the host 106 issues a shorter RPMB update data (e.g. 256 bytes) in a single frame, the controller 104 performs a first write process on the FLASH memory 102 to write the issued RPMB data and the write count of the RPMB corresponding thereto into a 1.sup.st allocated page in the FAT block RPMB_FAT and then performs a second write process on the FLASH memory 102 to write dummy data (or, further plus the write count the same as that of the first write process) into a 2.sup.nd allocated page in the FAT block RPMB FAT. When the host 106 issues a longer RPMB update data (e.g. 512 bytes) in two frames, the controller 104 writes the RPMB data issued in the two different frames separately”;
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAHIM BOURZIK whose telephone number is (571)270-7155. The examiner can normally be reached Monday-Friday (8-4:30).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wei Y Mui can be reached at 571-270-2738. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRAHIM BOURZIK/ Examiner, Art Unit 2191
/WEI Y MUI/ Supervisory Patent Examiner, Art Unit 2191