DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 04/27/2026.
Claims 1-16 are pending in this application.
Withdrawal of Restriction Requirement
2. Applicant’s remarks with respect to the restriction requirement of 02/25/2026 have been considered and found persuasive. The restriction requirement is henceforth withdrawn.
Acknowledges
3. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 04/11/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
4. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
5. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objection
6. The claim is objected to for the following reason:
In claim 2, line 2, the phrase “and the forming the insulation layer...” is unclear. It should be read as -- and the forming of the insulation layer... ---
Appropriate correction is required.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1, 6-12, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2003/0082875)
Regarding claim 1, Lee discloses a method for manufacturing a semiconductor structure, comprising:
providing a substrate 10 having a first surface (bottom surface; see figs. 2A, 2B) and a second surface (top surface proximate to source region 14) that are opposite to each other;
forming a transistor array positioned in the substrate from the first surface of the substrate, wherein the transistor array includes a plurality of transistors T, T1, T2 (fig. 1, fig. 2E), and a height of each transistor is less than a thickness of the substrate 10;
thinning the substrate 10 from the second surface until a first end of a conductive channel 12 of each transistor is exposed (see figs. 2B, 2C, and para. 0007), wherein the first end is an end, which is close to the second surface, of the conductive channel 12;
forming an insulation layer 29 & 31 covering at least a portion of the first end of the conductive channel 12, such that a first width of an exposed portion (a width of the conductive channel 12 exposed by contact holes 30, 32, para. 0008) of the first end of the conductive channel 12 is less than a second width (whole width) of the conductive channel 12; and
forming a bit line structure BL1, BL2 covering the exposed portion of the first end of the conductive channel 12.
Regarding claim 6, Lee discloses the method of claim 1, comprising:
providing a carrier wafer 24 (fig. 2E); and
bonding the first surface of the substrate and the carrier wafer 24.
Regarding claim 7, Lee discloses the method of claim 6, wherein the thinning the substrate from the second surface until the first end of the conductive channel 12 of the transistor is exposed comprises:
flipping the carrier wafer 24 and the substrate 10, such that the second surface is vertically upward; and
thinning the substrate 10 from the second surface until the first end of the conductive channel of the transistor is exposed. See figs. 2B, 2C.
Regarding claim 8, Kim discloses the method of claim 1, further comprising: forming, on the first surface of the substrate, a storage capacitor C1 connected to the transistor. See fig. 2B.
Regarding claim 9, Kim discloses the method of claim 1, further comprising:
forming a drain 25 at the first end of the conductive channel 12; and
forming a source 14 at a second end of the conductive channel, wherein the second end is an end, which is close to the first surface, of the conductive channel 12. See fig. 2E.
Regarding claim 10, Lee discloses a semiconductor structure, comprising:
a substrate 10 (see figs. 2A-2E), wherein the substrate has a first surface (source side 14 surface) and a second surface (drain side 25 surface) that are opposite to each other;
a transistor array positioned in the substrate 10, wherein the transistor array includes a plurality of transistors T, T1, T2, (figs. 1, 2E);
an insulation layer 29, 31 (fig. 2E), covering at least a portion of a first end of a conductive channel 12, such that a first width (a width of the conductive channel 12 exposed by contact holes 30, 32, para. 0008) of a portion of the first end of the conductive channel, which is not covered by the insulation layer 29, 31, is less than a second width (whole width) of the conductive channel 12, wherein the first end is an end, which is close to the second surface, of the conductive channel 12; and
a bit line structure BL1, BL2, connected to the (exposed) portion of the first end of the conductive channel 12, which is not covered by the insulation layer 29, 31.
Regarding claim 11, Kim discloses the semiconductor structure of claim 10, further comprising:
dielectric layers 16, 17 (figs. 2B, 2E, and para. 0006) positioned between the plurality of transistors; and
a plurality of recessed structures (formed by isotropically etching the oxide film 15, in which gate material 27 is filled, fig. 2D, and para. 0008) positioned between the dielectric layers 16, 17.
Regarding claim 12, Kim discloses the semiconductor structure of claim 11, wherein the insulation layer 26, 29 is positioned on a sidewall of the recessed structure, the insulation layer 26, 29 covers at least the portion of the first end of the conductive channel, and the recessed structure with the sidewall covered by the insulation layer is a trench. See fig. 2E.
Regarding claim 14, Kim discloses the semiconductor structure of claim 11, further comprising:
a word line structure 28 of the transistor, wherein the word line structure 28 is positioned between two adjacent conductive channels 12, the word line structure is positioned in a region of the recessed structure, and a depth of the recessed structure positioned on the word line structure 28 is less than a depth of the recessed structure positioned on the conductive channel 12. See fig. 2E.
Regarding claim 15, Kim discloses the semiconductor structure of claim 10, further comprising:
a storage capacitor 19-21, positioned on the first surface of the substrate and connected to the transistor. See fig. 2E.
Regarding claim 16, Kim discloses the semiconductor structure of claim 10, wherein the first end of the conductive channel comprises;
a drain of the transistor 25; and
a second end of the conductive channel comprises:
a source 14 of the transistor, and the second end is an end, which is close to the first surface, of the conductive channel 12. See fig. 2E.
Allowable Subject Matter
9. Claims 2-5, and 13 are allowable.
Claims 2-5, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form, to overcome the above objection (with respect to claims 2-5), and/or to include all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed method of manufacturing a semiconductor structure, or the claimed semiconductor structure (in addition to the other limitations in the claim) comprising:
Claims 2-5:
The method comprising:
continuing to etch, after the substrate is thinned, a portion of the conductive channel from the first end of the conductive channel, to form a plurality of recessed structures between the dielectric layers; and
forming the insulation layer on a sidewall of the recessed structure, such that the insulation layer covers at least the portion of the first end of the conductive channel to form a trench with a sidewall covered by the insulation layer.
Claim 13:
The semiconductor structure wherein the bit line structure is positioned in the trench, and a width of the trench is equal to the first width.
Conclusion
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 May 14, 2026
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