Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species IV in the reply filed on June 12, 2026 is acknowledged.
Drawings
The drawings are objected to because Fig. 17 appears to be missing labels, e.g. the dashed regions have no labels. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantial” in claim 1 is a relative term which renders the claim indefinite. The term “substantial” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Therefore, the use of the term "substantial" renders the limitation regarding the mirror symmetry indefinite as there is no parameter given for what constitutes "substantial mirror symmetry" in this case.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiao (Pub. No. CN 113327516 A).
Regarding claim 1, Xiao teaches an array substrate, comprising: a plurality of data lines (Figs. 1 and 2, data lines 1011; paragraphs n0031 & n0032); a plurality of second fanout connecting lines (Figs. 1 and 2, second fan-out traces 1022; paragraphs n0031 & n0032); and a plurality of first voltage supply lines (Fig. 2, VDD; paragraph n0030); wherein, in at least one subpixel of the array substrate, an individual data line of the plurality of data lines and an individual second fanout connecting line of the plurality of second fanout connecting lines have a substantial mirror symmetry with respect to an individual first voltage supply line of the plurality of first voltage supply lines (Fig. 2, driving circuit 20, data lines 1011, second fan-out traces 1022, VDD; paragraphs n0030-n0032 and n0039).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Zhou et al. (Pub. No. US 20240179970 A1), hereinafter referred to as Zhou.
Regarding claim 2, Xiao teaches the array substrate of claim 1 and further teaches the plurality of data lines and the plurality of second fanout connecting lines are in a same layer (Fig. 3, second fan-out trace 1022, data line 1011; ¶n0039). However, Xiao does not explicitly teach the plurality of first voltage supply lines also being in the same layer.
Zhou teaches the plurality of second fanout connecting lines and the plurality of first voltage supply lines are in a same layer (Fig. 3, first power supply signal lines 113, first fan-out lines 11; ¶47).
Xiao and Zhou are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teaches of Xiao with the teachings of Zhou to have the plurality of data lines, the plurality of second fanout connecting lines, and the plurality of first voltage supply lines in the same layer. For the purpose of increasing the flatness and symmetry of the device and reducing color shift of the display.
Claim(s) 3-5 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Wang et al. (Pub. No. WO 2021184305 A1), hereinafter referred to as Wang.
Regarding claim 3, Xiao teaches the array substrate of claim 1. Xiao further teaches a plurality of second fanout lines and that the second fanout lines are on the same layer as the plurality of data lines and that the plurality of fanout lines are arranged in equal intervals between the plurality of data lines (Figs. 2 and 3, second fan-out trace 1022, data line 1011; ¶n0039). However, Xiao does not explicitly teach the array substrate further comprising an anode on a side of the plurality of data lines, the plurality of second fanout connecting lines, and the plurality of first voltage supply lines away from a base substrate; wherein an orthographic projection of the anode on a base substrate at least partially overlaps with an orthographic projection of the individual second fanout connecting line on the base substrate; at least partially overlaps with an orthographic projection of the individual first voltage supply line on the base substrate; and at least partially overlaps with an orthographic projection of an individual data line on the base substrate.
Wang teaches the array substrate further comprising an anode on a side of the plurality of data lines and the plurality of first voltage supply lines away from a base substrate (Figs. 14 & 15, second electrode 212, first power signal line VDD1, data line Vd; lines 1351-1407); wherein an orthographic projection of the anode on a base substrate at least partially overlaps with an orthographic projection of the individual first voltage supply line on the base substrate (Figs. 14 & 15, second electrode 212, first power signal line VDD1; lines 1351-1407); and at least partially overlaps with an orthographic projection of an individual data line on the base substrate (Figs. 14 & 15, second electrode 212, data line Vd; lines 1351-1407).
Xiao and Wang are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang such that there is an anode on a side of the plurality of data lines, the plurality of second fanout connecting lines, and the plurality of first voltage supply lines away from a base substrate; wherein an orthographic projection of the anode on a base substrate at least partially overlaps with an orthographic projection of the individual second fanout connecting line on the base substrate; at least partially overlaps with an orthographic projection of the individual first voltage supply line on the base substrate; and at least partially overlaps with an orthographic projection of an individual data line on the base substrate. For the purpose of improving the flatness and symmetry of the device and reducing color shift.
Regarding claim 4, Xiao further teaches the individual second fanout connecting line and the individual data line are substantially evenly distributed along a first direction (Figs. 2 and 3, second fan-out trace 1022, data line 1011; ¶n0039). However, Xiao does not explicitly teach the individual second fanout connecting line, the individual first voltage supply line, and the individual data line are substantially evenly distributed along a first direction with respect to the anode.
Wang teaches the individual first voltage supply line and the individual data line are substantially evenly distributed along a first direction with respect to the anode (Figs. 14 & 15, second electrode 212, first power signal line VDD1, data line Vd; lines 1351-1407).
Xiao and Wang are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang such that the individual second fanout connecting line, the individual first voltage supply line, and the individual data line are substantially evenly distributed along a first direction with respect to the anode. For the purpose of improving the flatness and symmetry of the device and reducing color shift.
Regarding claim 5, Xiao further teaches the second fanout connecting lines having substantial mirror an individual data line of the plurality of data lines and an individual second fanout connecting line of the plurality of second fanout connecting lines have a substantial mirror symmetry with respect to an individual first voltage supply line of the plurality of first voltage supply lines (Fig. 2, data lines 1011, second fan-out traces 1022, VDD; paragraphs n0030-n0032 and n0039). However, Xiao does not explicitly teach portions of the individual second fanout connecting line, the individual first voltage supply line, and the individual data line, in a region crossing over the anode, have a substantial mirror symmetry with respect to a plane perpendicular to the anode and intersecting the anode.
Wang teaches portions of the individual first voltage supply line and the individual data line, in a region crossing over the anode, have a substantial mirror symmetry with respect to a plane perpendicular to the anode and intersecting the anode (Figs. 14 & 15, second electrode 212, first power signal line VDD1, data line Vd; lines 1351-1407).
Xiao and Wang are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang such that portions of the individual second fanout connecting line, the individual first voltage supply line, and the individual data line, in a region crossing over the anode, have a substantial mirror symmetry with respect to a plane perpendicular to the anode and intersecting the anode. For the purpose of improving the flatness and symmetry of the device and reducing color shift.
Regarding claim 11, Xiao does not explicitly teach the array substrate comprising an anode, an anode connecting pad, a second relay electrode, and a first relay electrode; a first anode connecting via, a second anode connecting via, a third anode connecting via, and a fourth anode connecting via; and a pixel driving circuit comprising a light emitting control transistor; wherein the anode is connected to the anode connecting pad through the first anode connecting via; the anode connecting pad is connected to the second relay electrode through the second anode connecting via; the second relay electrode is connected to the first relay electrode through the third anode connecting via; and the first relay electrode is connected to a second electrode of the light emitting control transistor through the fourth anode connecting via.
Wang teaches an anode, an anode connecting pad, a second relay electrode, and a first relay electrode; a first anode connecting via, a second anode connecting via, a third anode connecting via, and a fourth anode connecting via; and a pixel driving circuit comprising a light emitting control transistor; wherein the anode is connected to the anode connecting pad through the first anode connecting via; the anode connecting pad is connected to the second relay electrode through the second anode connecting via; the second relay electrode is connected to the first relay electrode through the third anode connecting via; and the first relay electrode is connected to a second electrode of the light emitting control transistor through the fourth anode connecting via (Fig. 9E, second electrode 212, first main body electrode 2121, first connection electrode 2122, second part 3432, first via hole 3541, second electrode 222, second via hole 3543, second electrode 232, third main body part 2321, third connection electrode 2322, third via hole 3543, third connection portion 343; lines 1037-1053).
Xiao and Wang are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang such that the device includes an anode, an anode connecting pad, a second relay electrode, and a first relay electrode; a first anode connecting via, a second anode connecting via, a third anode connecting via, and a fourth anode connecting via; and a pixel driving circuit comprising a light emitting control transistor; wherein the anode is connected to the anode connecting pad through the first anode connecting via; the anode connecting pad is connected to the second relay electrode through the second anode connecting via; the second relay electrode is connected to the first relay electrode through the third anode connecting via; and the first relay electrode is connected to a second electrode of the light emitting control transistor through the fourth anode connecting via. For the purpose ensuring the electrical functionality and mechanical stability of the device.
Regarding claim 12, Xiao does not explicitly teach a first adjacent column of pixel driving circuits, the first anode connecting via is spaced apart from the fourth anode connecting via by a first distance along a second direction; in a second adjacent column of pixel driving circuits, the first anode connecting via is spaced apart from the fourth anode connecting via by a second distance along the second direction; and the second distance is greater than the first distance by at least 10%.
Wang teaches a first adjacent column of pixel driving circuits, the first anode connecting via is spaced apart from the fourth anode connecting via by a first distance along a second direction; in a second adjacent column of pixel driving circuits, the first anode connecting via is spaced apart from the fourth anode connecting via by a second distance along the second direction; and the second distance is greater than the first distance by at least 10% (Figs. 5 and 6, third via 3543, first sub-via 3452-1; lines 1061-1079, 1240-1261).
Xiao and Wang are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang such that in a first adjacent column of pixel driving circuits, the first anode connecting via is spaced apart from the fourth anode connecting via by a first distance along a second direction; in a second adjacent column of pixel driving circuits, the first anode connecting via is spaced apart from the fourth anode connecting via by a second distance along the second direction; and the second distance is greater than the first distance by at least 10%. For the purpose of improving the flatness and symmetry of the device and reducing color shift.
Claim(s) 6, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Wang and further in view of Lee et al. (Pub. No. US 20230247863 A1), hereinafter referred to as Lee.
Regarding claim 6, Xiao teaches the array substrate of claim 1. However, Xiao does not explicitly teach a first data signal connecting pad, a second data signal connecting pad, and a fanout connecting pad; wherein the individual data line is connected to the second data signal connecting pad through a first pad connecting via; the individual second fanout connecting line is connected to the fanout connecting pad through a second pad connecting via; and the second data signal connecting pad is connected to the first data signal connecting pad through a third pad connecting via.
Wang teaches including a first and second pad block and connecting vias (first block 344, via hole 3440, second pad block 345, via hole 381; lines 841-850, 976-1004, 1473-1505, 1630-1639, 1665-1669).
Xiao and Wang are analogous art as they are in the same field of endeavor of semiconductors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang to include connecting pads and connecting vias such that the array substrate comprises a first data signal connecting pad and a second data signal connecting pad; wherein the individual data line is connected to the second data signal connecting pad through a first pad connecting via; and the second data signal connecting pad is connected to the first data signal connecting pad through a third pad connecting via. For the purpose ensuring the electrical functionality and mechanical stability of the device. However, Xiao in view of Wang still does not teach a fanout connecting pad.
Lee teaches the fanout connecting pad (Fig. 22, data pad unit 20, first connection line CL1, second connection line CL2, third connection line CL3; ¶284-288).
Xiao, Wang, and Lee are all analogous art as they are in the same field of endeavor of semiconductors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao in view of Wang with the teachings of Lee such that the array substrate includes a fanout connecting pad and the individual second fanout connecting line is connected to the fanout connecting pad through a second pad connecting via. For the purpose ensuring the electrical functionality and mechanical stability of the device.
Regarding claim 9, Xiao does not explicitly teach a pixel definition layer; wherein an orthographic projection of the pixel definition layer on a base substrate covers an orthographic projection of a conductive material extending through the first pad connecting via on the base substrate and covers an orthographic projection of a conductive material extending through the second pad connecting via on the base substrate.
Wang teaches a pixel definition layer; wherein an orthographic projection of the pixel definition layer on a base substrate covers an orthographic projection of a conductive material extending through the first pad connecting via on the base substrate and covers an orthographic projection of a conductive material extending through the second pad connecting via on the base substrate (Fig. 11-13, via hole 3440, base substrate 100, second electrode 212, first color sub-pixel, light emitting region 2100; lines 110-114, 598-613, 1112-1166, 1489-1496).
Xiao, Wang, and Lee are all analogous art as they are in the same field of endeavor of semiconductors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang such that the device includes a pixel definition layer; wherein an orthographic projection of the pixel definition layer on a base substrate covers an orthographic projection of a conductive material extending through the first pad connecting via on the base substrate and covers an orthographic projection of a conductive material extending through the second pad connecting via on the base substrate. For the purpose of not affecting the display of the color sub-pixels, as recognized by Wang.
Regarding claim 10, Xiao does not explicitly teach comprising a pixel definition layer defining a plurality of subpixel apertures, and a light emitting layer in the plurality of subpixel apertures; wherein an orthographic projection of a light emitting material in the plurality of subpixel apertures on a base substrate is substantially non-overlapping with the orthographic projection of a conductive material extending through the first pad connecting via on the base substrate, and is non-overlapping with the orthographic projection of a conductive material extending through the second pad connecting via on the base substrate.
Wang teaches comprising a pixel definition layer defining a plurality of subpixel apertures, and a light emitting layer in the plurality of subpixel apertures; wherein an orthographic projection of a light emitting material in the plurality of subpixel apertures on a base substrate is substantially non-overlapping with the orthographic projection of a conductive material extending through the first pad connecting via on the base substrate, and is non-overlapping with the orthographic projection of a conductive material extending through the second pad connecting via on the base substrate (Fig. 11-13, via hole 3440, base substrate 100, second electrode 212, first color sub-pixel, light emitting region 2100; lines 110-114, 598-613, 1112-1166, 1489-1496).
Xiao, Wang, and Lee are all analogous art as they are in the same field of endeavor of semiconductors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Wang such that the device includes a pixel definition layer defining a plurality of subpixel apertures, and a light emitting layer in the plurality of subpixel apertures; wherein an orthographic projection of a light emitting material in the plurality of subpixel apertures on a base substrate is substantially non-overlapping with the orthographic projection of a conductive material extending through the first pad connecting via on the base substrate, and is non-overlapping with the orthographic projection of a conductive material extending through the second pad connecting via on the base substrate. For the purpose of not affecting the display of the color sub-pixels, as recognized by Wang.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Wang and Lee as applied to claim 6 above, and further in view of Yuan et al. (US 20230043145 A1), hereinafter referred to as Yuan.
Regarding claim 7, Xiao in view of Wang and Lee does not explicitly teach an orthographic projection of a conductive material extending through the first pad connecting via on a base substrate is substantially non-overlapping with an orthographic projection of a conductive material extending through the third pad connecting via on the base substrate.
Yuan teaches an orthographic projection of a conductive material extending through the first pad connecting via on a base substrate is substantially non-overlapping with an orthographic projection of a conductive material extending through the third pad connecting via on the base substrate (Fig. 9, first vias 11; ¶49).
Xiao, Wang, Lee, and Yuan are all analogous art as they are in the same field of endeavor of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao in view of Wang and Lee with the teachings of Yuan such that an orthographic projection of a conductive material extending through the first pad connecting via on a base substrate is substantially non-overlapping with an orthographic projection of a conductive material extending through the third pad connecting via on the base substrate. For the purpose of avoiding the problem of a poor display panel caused by a concentrated distribution of vias, as recognized by Yuan.
Regarding claim 8, Xiao in view of Yuan and Lee does not explicitly teach the first pad connecting via has a first elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the second pad connecting via has a second elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the third pad connecting via has a third elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the first elongated shape has a longitudinal side along a direction substantially parallel to a first direction; the second elongated shape has a longitudinal side along a direction substantially parallel to the first direction; and the third elongated shape has a longitudinal side along a direction substantially parallel to a second direction.
Yuan teaches the first pad connecting via has a first elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the second pad connecting via has a second elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the third pad connecting via has a third elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the first elongated shape has a longitudinal side along a direction substantially parallel to a first direction; the second elongated shape has a longitudinal side along a direction substantially parallel to the first direction; and the third elongated shape has a longitudinal side along a direction substantially parallel to a second direction (Fig. 9, date lines 1, fan-out traces 2, vias 11; ¶48-49).
Xiao, Wang, Lee, and Yuan are all analogous art as they are in the same field of endeavor of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao in view of Wang and Lee with the teachings of Yuan such that the first pad connecting via has a first elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the second pad connecting via has a second elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the third pad connecting via has a third elongated shape in a cross-section along a plane having the plurality of data lines, the plurality of first voltage supply lines, and the plurality of second fanout connecting lines; the first elongated shape has a longitudinal side along a direction substantially parallel to a first direction; the second elongated shape has a longitudinal side along a direction substantially parallel to the first direction; and the third elongated shape has a longitudinal side along a direction substantially parallel to a second direction. For the purpose ensuring the electrical functionality and mechanical stability of the device.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Wang as applied to claim 11 above, and further in view of Shang et al. (Pub. No. WO 2021189305 A1), hereinafter referred to as Shang.
Regarding claim 13, Xiao in view of Wang does not explicitly teach in a first adjacent column of pixel driving circuits, an orthographic projection of the anode on a base substrate substantially covers the orthographic projection of the anode connecting pad on a base substrate, substantially covers the orthographic projection of the second relay electrode on the base substrate, and substantially covers the orthographic projection of the first relay electrode on the base substrate; and in a second adjacent column of pixel driving circuits, an orthographic projection of the anode on the base substrate partially overlaps with an orthographic projection of the anode connecting pad on the base substrate, is substantially non-overlapping with the orthographic projection of the second relay electrode on the base substrate, and is substantially non- overlapping with the orthographic projection of the first relay electrode on the base substrate.
Shang teaches in a first adjacent column of pixel driving circuits, an orthographic projection of the anode on a base substrate substantially covers the orthographic projection of the anode connecting pad on a base substrate, substantially covers the orthographic projection of the second relay electrode on the base substrate, and substantially covers the orthographic projection of the first relay electrode on the base substrate; and in a second adjacent column of pixel driving circuits, an orthographic projection of the anode on the base substrate partially overlaps with an orthographic projection of the anode connecting pad on the base substrate, is substantially non-overlapping with the orthographic projection of the second relay electrode on the base substrate, and is substantially non- overlapping with the orthographic projection of the first relay electrode on the base substrate (Fig. 7, first anode 1751, second anode 1752, third anode 1753, anode pair 1755, fourth anode 1754, first conductive portion 1621, second conductive portion 1622, third conductive portion 1623, fourth conductive portion 1624; lines 744-791).
Xiao, Wang, and Shang are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xiao in view of Wang with the teachings of Shang such that in a first adjacent column of pixel driving circuits, an orthographic projection of the anode on a base substrate substantially covers the orthographic projection of the anode connecting pad on a base substrate, substantially covers the orthographic projection of the second relay electrode on the base substrate, and substantially covers the orthographic projection of the first relay electrode on the base substrate; and in a second adjacent column of pixel driving circuits, an orthographic projection of the anode on the base substrate partially overlaps with an orthographic projection of the anode connecting pad on the base substrate, is substantially non-overlapping with the orthographic projection of the second relay electrode on the base substrate, and is substantially non- overlapping with the orthographic projection of the first relay electrode on the base substrate. For the purpose of improving the flatness of the device and reducing color shift, as recognized by Shang.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Wang et al (Pub. No. US 20210126075 A1), hereinafter referred to as Wang (US 2021).
Regarding claim 14, Xiao teaches the array substrate of claim 1, however Xiao does not explicitly teach in a first adjacent column of pixel driving circuits, a respective reference signal line of a plurality of reference signal lines; and in a second adjacent column of pixel driving circuits, a respective third reset signal line of a plurality of third reset signal lines; wherein the plurality of reference signal lines are absent in the second adjacent column of pixel driving circuits; and the plurality of third reset signal lines are absent in the first adjacent column of pixel driving circuits.
Wang (US 2021) teaches in a first adjacent column of pixel driving circuits, a respective reference signal line of a plurality of reference signal lines; and in a second adjacent column of pixel driving circuits, a respective third reset signal line of a plurality of third reset signal lines; wherein the plurality of reference signal lines are absent in the second adjacent column of pixel driving circuits; and the plurality of third reset signal lines are absent in the first adjacent column of pixel driving circuits (Fig. 2, Sub-pixels(n), Sub-pixels(n+1), power signal line VDD, reset signal line VI; ¶29-25).
Xiao and Wang (US 2021) are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xiao with the teachings of Wang (US 2021) such that in a first adjacent column of pixel driving circuits, a respective reference signal line of a plurality of reference signal lines; and in a second adjacent column of pixel driving circuits, a respective third reset signal line of a plurality of third reset signal lines; wherein the plurality of reference signal lines are absent in the second adjacent column of pixel driving circuits; and the plurality of third reset signal lines are absent in the first adjacent column of pixel driving circuits. For the purpose of having more room for increasing pixels per inch (PPI) for creating high PPI panel designs, as recognized by Wang (US 2021).
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Wang (US 2021) as applied to claim 14 above, and further in view of Wang.
Regarding claim 15, Xiao in view of Wang (US 2021) does not explicitly teach a node connecting line in a respective pixel driving circuit; wherein, in the first adjacent column of pixel driving circuits, the node connecting line is at least partially surrounded by the respective reference signal line.
Wang teaches a node connecting line in a respective pixel driving circuit; wherein, in the first adjacent column of pixel driving circuits, the node connecting line is at least partially surrounded by the respective reference signal line (Figs. 8, 9A-9D, and 10, first connection portion 341, rest control signal line Rst; lines 805-1004).
Xiao, Wang (US 2021), and Wang are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xiao in view of Wang (US 2021) with the teachings of Wang such that the device includes a node connecting line in a respective pixel driving circuit; wherein, in the first adjacent column of pixel driving circuits, the node connecting line is at least partially surrounded by the respective reference signal line. For the purpose ensuring the electrical functionality and mechanical stability of the device.
Regarding claim 16, Xiao in view of Wang (US 2021) does not explicitly teach in the first adjacent column of pixel driving circuits, the respective reference signal line comprises a main body extending along a direction substantially parallel to a second direction, and a plurality of first reference signal branches; a respective first reference signal branch of the plurality of first reference signal branches extends away from the main body; the respective first reference signal branch comprises a first portion and a second portion; the first portion connects the second portion with the main body; the first portion extends along a direction substantially parallel to a first direction; the second portion extends along a direction substantially parallel to the second direction; and the node connecting line is at least partially surrounded by the main body on a first side, by the first portion on a second side, and by the second portion on a third side.
Wang teaches in the first adjacent column of pixel driving circuits, the respective reference signal line comprises a main body extending along a direction substantially parallel to a second direction, and a plurality of first reference signal branches; a respective first reference signal branch of the plurality of first reference signal branches extends away from the main body; the respective first reference signal branch comprises a first portion and a second portion; the first portion connects the second portion with the main body; the first portion extends along a direction substantially parallel to a first direction; the second portion extends along a direction substantially parallel to the second direction; and the node connecting line is at least partially surrounded by the main body on a first side, by the first portion on a second side, and by the second portion on a third side (Fig. 11 and 13, first power signal line VDD1, second power signal line VDD2, first electrode CC1; lines 1466-1492).
Xiao, Wang (US 2021), and Wang are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xiao in view of Wang (US 2021) with the teachings of Wang such that in the first adjacent column of pixel driving circuits, the respective reference signal line comprises a main body extending along a direction substantially parallel to a second direction, and a plurality of first reference signal branches; a respective first reference signal branch of the plurality of first reference signal branches extends away from the main body; the respective first reference signal branch comprises a first portion and a second portion; the first portion connects the second portion with the main body; the first portion extends along a direction substantially parallel to a first direction; the second portion extends along a direction substantially parallel to the second direction; and the node connecting line is at least partially surrounded by the main body on a first side, by the first portion on a second side, and by the second portion on a third side. For the purpose ensuring the electrical functionality and mechanical stability of the device.
Regarding claim 17, Xiao in view of Wang (US 2021) does not explicitly teach in the second adjacent column of pixel driving circuits, the node connecting line is at least partially surrounded by the respective third reset signal line on a first side, and at least partially surrounded by a first voltage signal connecting pad on a second side.
Wang teaches in the second adjacent column of pixel driving circuits, the node connecting line is at least partially surrounded by the respective third reset signal line on a first side, and at least partially surrounded by a first voltage signal connecting pad on a second side.
(Fig. 13, rest control signal line Rst, strip-shaped body portion 3441, protrusion 3442, first pad 344, first connection portion 341; lines 1466-1492).
Xiao, Wang (US 2021), and Wang are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xiao in view of Wang (US 2021) with the teachings of Wang such that in the second adjacent column of pixel driving circuits, the node connecting line is at least partially surrounded by the respective third reset signal line on a first side, and at least partially surrounded by a first voltage signal connecting pad on a second side. For the purpose ensuring the electrical functionality and mechanical stability of the device.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Lee.
Regarding claim 18, Xiao teaches the array substrate of claim 1, a plurality of first fanout connecting lines (Fig. 1, first fan-out routing lines 1021; paragraph n0032), and the respective second fanout connecting line is electrically connected to a data driving circuit (Fig. 2, second fanout routing lines 1022, driving circuit 20; paragraphs n0029 & n0030). However Xiao does not explicitly teach, a second data signal connecting pad, a fanout connecting pad, a first connecting bridge, and a second connecting bridge; wherein the plurality of data lines comprises a plurality of second data lines; a respective second data line of the plurality of second data lines is connected to the second data signal connecting pad; the second data signal connecting pad is connected to the second connecting bridge; the second connecting bridge is connected to a respective first fanout connecting line of the plurality of first fanout connecting lines; the respective first fanout connecting line is connected to the first connecting bridge; the first connecting bridge is connected to a respective second fanout connecting line of the plurality of second fanout connecting lines.
Lee teaches a plurality of first fanout connecting lines, a second data signal connecting pad, a fanout connecting pad, a first connecting bridge, and a second connecting bridge (Fig. 22, third connection line second portion CL3b, data pad unit 20, connection line first portion CL3a, second connection line CL2; ¶284-288); wherein the plurality of data lines comprises a plurality of second data lines (Fig. 22, second data lines DL2; ¶284-288 ); a respective second data line of the plurality of second data lines is connected to the second data signal connecting pad (Fig. 22, second data line DL2, data pad unit 20; ¶284-288); the second data signal connecting pad is connected to the second connecting bridge (Fig. 22, data pad unit 20, second connection line CL2; ¶284-288); the second connecting bridge is connected to a respective first fanout connecting line of the plurality of first fanout connecting lines (Fig. 22, second connection line CL2, third connection line CL3; ¶284-288); the respective first fanout connecting line is connected to the first connecting bridge (Fig. 22, connection line first portion CL3a, third connection line second portion CL3b; ¶284-288); the first connecting bridge is connected to a respective second fanout connecting line of the plurality of second fanout connecting lines (Fig. 22, connection line second portion CL3b, first connection line CL1; ¶284-288); and the respective second fanout connecting line is electrically connected to a data driving circuit (Fig. 22, first connection line CL1, data pad unit 20; ¶284-288).
Xiao and Lee are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xiao with the teachings of Lee such that the device includes a plurality of first fanout connecting lines, a second data signal connecting pad, a fanout connecting pad, a first connecting bridge, and a second connecting bridge; wherein the plurality of data lines comprises a plurality of second data lines; a respective second data line of the plurality of second data lines is connected to the second data signal connecting pad; the second data signal connecting pad is connected to the second connecting bridge; the second connecting bridge is connected to a respective first fanout connecting line of the plurality of first fanout connecting lines; the respective first fanout connecting line is connected to the first connecting bridge; the first connecting bridge is connected to a respective second fanout connecting line of the plurality of second fanout connecting lines; and the respective second fanout connecting line is electrically connected to a data driving circuit. For the purpose ensuring the electrical functionality and mechanical stability of the device.
Claim(s) 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao in view of Mi et al. (US Patent No. US 12,557,676 B2), hereinafter referred to as Mi.
Regarding claim 20, Xiao teaches an array substrate, comprising: a plurality of data lines (Fig. 1, data lines 1011; paragraphs n0031 & n0032); a plurality of first fanout connecting lines (Fig. 1, first fan-out routing lines 1021; paragraph n0032); a plurality of second fanout connecting lines (Fig. 1, second fan-out routing line 1022; paragraph n0031 & n0032); and a plurality of first voltage supply lines (Fig. 2, VDD; paragraph n0030); wherein, in at least one subpixel of the array substrate, an individual data line of the plurality of data lines and an individual second fanout connecting line of the plurality of second fanout connecting lines have a substantial mirror symmetry with respect to an individual first voltage supply line of the plurality of first voltage supply lines (Fig. 2, driving circuit 20, data lines 1011, second fan-out traces 1022, VDD; paragraphs n0030-n0032 and n0039); the plurality of first fanout connecting lines and the plurality of second fanout connecting lines are substantially in a display area of the array substrate (Fig. 1, display area 100, fan-out routing line 102, first fan-out routing lines 1021, second fan-out routing line 1022; paragraph n0028). However, Xiao does not explicitly teach the plurality of data lines comprise a plurality of first data lines and a plurality of second data lines; the plurality of first data lines are connected to a data driving circuit; and a respective second data line of the plurality of second data lines is connected to the data driving circuit through a respective first fanout connecting line of the plurality of first fanout connecting lines and a respective second fanout connecting line of the plurality of second fanout connecting lines.
Mi teaches the plurality of data lines comprise a plurality of first data lines and a plurality of second data lines (Figs. 2 & 3, first data lines 24, second data lines 25; Col. 3, line 53 - Col. 6 line 35); the plurality of first data lines are connected to a data driving circuit (functional area 23, first data lines 24; Col. 3, line 53 - Col. 6 line 35); and a respective second data line of the plurality of second data lines is connected to the data driving circuit through a respective first fanout connecting line of the plurality of first fanout connecting lines and a respective second fanout connecting line of the plurality of second fanout connecting lines (functional area 23, second data lines 25, second connecting line 27, first connecting line segment 271, second connecting line segment 272; Col. 3, line 53 - Col. 6 line 35).
Xiao and Mi are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Mi such that the plurality of data lines comprise a plurality of first data lines and a plurality of second data lines; the plurality of first data lines are connected to a data driving circuit; and a respective second data line of the plurality of second data lines is connected to the data driving circuit through a respective first fanout connecting line of the plurality of first fanout connecting lines and a respective second fanout connecting line of the plurality of second fanout connecting lines. For the purpose of having a narrower frame and reducing manufacturing costs, as recognized by Mi.
Regarding claim 21, Xiao teaches the array substrate of claim 1 and further teaches a display apparatus, comprising the array substrate of claim 1 (n0044). However, Xiao does not explicitly teach one or more integrated circuits connected to the array substrate.
Mi teaches one or more integrated circuits connected to the array substrate (Figs. 2 & 3, functional area 23; Col. 3 lines 53-67).
Xiao and Mi are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify the structure of Xiao with the teachings of Mi such that there are one or more integrated circuits connected to the array substrate. For the purpose of packaging the device in a Chip On Glass (COG) package, as recognized by Mi.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (US 20210313498 A1), Shang et al. (US 12,284,885 B2), Wang et al. (US 12,225,789 B2), Liu et al. (WO 2021097754), Wu et al. (WO 2021102995 A1), and Yang et al. (WO 2021189875 A1).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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