Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed July 21, 2026, has been entered. Claims 13-24 remain pending in the application and claims 25 and 26 are newly added. Applicant’s amendments to the claims have overcome each and every claim objection previously set forth and amendments to the specification have overcome the objection to the typographical error in paragraph 4 as previously set forth in the Non-Final Office Action mailed March 24, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 13 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 13, the amendment adds the limitation “wherein a value of a sheet resistance of said semiconductor structure does not differ between an edge of said wafer or close to a center of said wafer”. Applicant cites paragraphs 65 and 67 of the specification supporting such limitation. However, the specification does not seem to disclose the sheet resistance not differing between an edge of the wafer or close to the center of the wafer. In fact, as disclosed in Fig. 3B, paragraph 67 of the specification, and claim 25, the sheet resistance varies in the range of 225 Ω/sq to 230 Ω/sq along a radius of the wafer.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 22-24 and 26 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Yamada (Pub. No. 20180145148 A1).
Regarding claim 22, Yamada teaches a method for manufacturing a semiconductor structure, wherein said method comprises the steps of: providing a substrate; providing an epitaxial III-N semiconductor layer stack on top of said substrate; wherein providing said epitaxial III-N semiconductor layer stack comprises the steps of: providing a first active III-N layer; providing a spacer layer on top of said first active III-N layer, wherein said spacer layer comprises Aluminum Nitride; providing a diffusion barrier layer on top of said spacer layer, wherein said diffusion barrier layer comprises Gallium Nitride; and wherein a thickness of said diffusion barrier layer is less than 1nm; providing a second active III-N layer on top of and in direct contact with said diffusion barrier layer; wherein said second active III-N layer comprises Indium Aluminum Nitride; thereby forming a two-dimensional Electron Gas between said first active III-N layer and said second active III-N layer (See Non-Final Office Action Dated March 24, 2026). Yamada further teaches wherein said manufacturing said semiconductor structure corresponds to epitaxially growing said semiconductor structure on a wafer (¶40-47); and wherein said method further comprises a step of thermally annealing said semiconductor structure (Fig. 6C; ¶49).
Regarding claim 23, Yamada teaches a method for manufacturing a high electron mobility transistor, wherein said method comprises the steps of: providing a substrate; providing an epitaxial III-N semiconductor layer stack on top of said substrate; wherein providing said epitaxial III-N semiconductor layer stack comprises the steps of: providing a first active III-N layer; providing a spacer layer on top of said first active III-N layer, wherein said spacer layer comprises Aluminum Nitride; providing a diffusion barrier layer on top of said spacer layer, wherein said diffusion barrier layer comprises Gallium Nitride; and wherein a thickness of said diffusion barrier layer is less than 1nm; providing a second active III-N layer on top of and in direct contact with said diffusion barrier layer; wherein said second active III-N layer comprises Indium Aluminum Nitride; thereby forming a two-dimensional Electron Gas between said first active III-N layer and said second active III-N layer, thereby forming a semiconductor structure; and providing a gate contact in direct contact with said second active III-N layer in a gate region (See Non-Final Office Action Dated March 24, 2026). Yamada further teaches wherein said manufacturing said semiconductor structure corresponds to epitaxially growing said semiconductor structure on a wafer (¶40-47); and wherein said method further comprises a step of thermally annealing said semiconductor structure (Fig. 6C; ¶49).
Regarding claim 24, Yamada teaches all the limitations of claim 24 as detailed in the Non-Final Office Action dated March 24, 2026.
Regarding claim 26, Yamada further teaches wherein said thermally annealing said semiconductor structure corresponds to thermally annealing said semiconductor structure at 750°C (Fig. 6C; ¶49).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 13-19, 21, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Derluyn et al. (US Patent No. 8,809,138), hereinafter referred to as Derluyn.
Regarding claim 13, Yamada teaches a semiconductor structure comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; a spacer layer on top of said first active III-N layer, wherein said spacer layer comprises Aluminum Nitride; a diffusion barrier layer on top of said spacer layer; a second active III-N layer on top of and in direct contact with said diffusion barrier layer, wherein said second active III-N layer comprises Indium Aluminum Nitride; with a two-dimensional Electron Gas between said first active III-N layer and said second active III-N layer; wherein said diffusion barrier layer comprises Gallium Nitride; and wherein a thickness of said diffusion barrier layer is less than 1nm (See Non-Final Office Action Dated March 24, 2026). Yamada further teaches wherein said semiconductor structure is epitaxially grown on a wafer (¶40-44). However, Yamada does not teach a value of a sheet resistance of said semiconductor structure does not differ between an edge of said wafer or close to a center of said wafer.
Derluyn teaches a value of a sheet resistance of said semiconductor structure does not differ between an edge of said wafer or close to a center of said wafer (Fig. 13, Col. 16, line 49 – Col. 17, line 19).
Yamada and Derluyn are analogous art as they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date to modify Yamada with the teachings of Derluyn such that a value of a sheet resistance of said semiconductor structure does not differ between an edge of said wafer or close to a center of said wafer. For the purpose of preventing degradation of the device during annealing processes and to ensure reliable functionality of the device, as recognized by Derluyn
Regarding claims 14-19 and 21, Yamada further teaches the limitations of claims 14-19 and 21 as detailed in the Non-Final Office Action dated March 24, 2026.
Regarding claim 25, Yamada further teaches wherein said sheet resistance is in the range of 225 Ω/sq to 230 Ω/sq along a radius of said wafer (Figs. 2 & 3; ¶37-38).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Derluyn as applied to claim 1 above, and further in view of Nozaki (Pub. No. JP 2008198783 A).
Regarding claim 20, Yamada in view of Nozaki teaches the limitations of claim 20 as detailed in the Non-Final Office Action dated March 24, 2026.
Response to Arguments
Applicant's arguments filed July 21, 2026 have been fully considered but they are not persuasive.
Regarding specification objections directed to paragraphs 69-72 (See Applicant’s response, page 10, “Specification”), Examiner appreciates Applicant’s response as it has helped to clarify the issue and Examiner acknowledges that the section is not erroneous. However, Applicant fails to address the issue then seems to be directed to the use of “the semiconductor structure 1” in the sentence “According to an optional example embodiment, the semiconductor structure 1 further comprises a passivation layer 300 formed on top of the second active III-N structure 204”. As paragraphs 69-72 are directed to descriptions of Figs. 5-8 which are directed to “high electron mobility transistor 2” and are not directed to “semiconductor structure 1” which is referenced in Fig. 2. It seems likely that there was a typographical error and that “semiconductor structure 1” should be changed to “high electron mobility transistor 2”, or if that’s not the case then the sentence likely needs rephrasing to improve clarity. Therefore, specification objections directed to paragraphs 69-72 is being maintained.
Regarding independent claims 13, 22, and 23 (See Applicant’s response, pages 10-13, “Claim Rejections – 35 U.S.C. §102”), Applicant argues that Yamada fails to disclose a spacer layer comprising Aluminum Nitride and that Yamada does not teach the advantages of using Aluminum Nitride and instead teaches away from the use of Aluminum Nitride. Firstly, Yamada discloses a spacer layer comprising Aluminum Nitride, as Yamada teaches the use of a AlGaN spacer layer (¶42). Under a broadest reasonable interpretation, the term “comprising” is inclusive or open-ended and does not exclude additional unrecited elements (MPEP §2111.03(I)). Therefore, an AlGaN spacer layer falls within the claim scope of a spacer layer comprising AlN. Furthermore, Examiner agrees that Yamada teaches that it is difficult to grow an AlN layer flat. However, a known or obvious composition does not become patentable simply because it has been described as somewhat inferior to some other product for the same use (MPEP §2145D(I)). The use of AlN layers in high electron mobility transistors (HEMT) is well known in the art, as for example both Derluyn (¶30) and Nozaki (Abstract) also both disclose the use of an AlN layer. Therefore, while Yamada does teach a disadvantage to using an AlN layer it would have been known to one of ordinary skill in the art that an AlN layer could have been used regardless of the disadvantage disclosed by Yamada.
Applicant further argues that Yamada does not teach the amended feature to claim 13 “a value of sheet resistance of said semiconductor structure does not differ between an edge of said wafer or close to a center of said wafer”. Examiner agrees that Yamada is silent on this feature. However, as detailed in the above section “Claim Rejections - 35 USC § 112” the specification of the instant application does not teach this feature and in fact, as disclosed in Fig. 3B, paragraph 67 of the specification, and claim 25, the instant application teaches that the sheet resistance is in the range of 225 Ω/sq to 230 Ω/sq along a radius of the wafer. However, for the purposes of examination and compact prosecution the rejection under 35 U.S.C. §102 is withdrawn for claims 13-19 and 21 and a new ground(s) of rejection under 35 U.S.C. §103 for claims 13-19 and 21 is made due to the amendment to claim 13. The details of said rejection are detailed in the above section “Claim Rejections - 35 USC § 103”.
Applicant also argues that Yamada fails to disclose the amended feature to claims 22 and 23 “said method further comprises a step of thermally annealing said semiconductor structure”. However, Yamada does disclose a step of thermally annealing said semiconductor structure (Fig. 6C; ¶49). Therefore, the rejection under 35 U.S.C. §102 for claims 22-24 are maintained.
Regarding claim 20 (See Applicant’s response, pages 14, “Claim Rejections – 35 U.S.C. §103”), Applicant argues that claim 20 is patentable as claim 13 is patentable, however as claim 13 remains rejected claim 20 also remains rejected. However, a new ground(s) of rejection under 35 U.S.C. §103 for claim 20 is made due to the amendment to claim 13. The details of said rejection are detailed in the above section “Claim Rejections - 35 USC § 103”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
