Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Paragraph 4 contains “Ternary InAlN layers have the potential to replace conventional AlGaN as th e barrier layer.” Seems to be a typographical error and “th e” should likely read “the”.
Paragraph 69 contains the following “According to an optional example embodiment, the semiconductor structure 1 further comprises a passivation layer 300 formed on top of the second active III-N structure 204. According to an optional example embodiment, the passivation layer 300 comprises Silicon Nitride and/or an oxide layer. According to an alternative embodiment, the passivation layer 300 comprises Gallium Nitride. According to a further alternative embodiment, the passivation layer 300 comprises Gallium Nitride and Silicon Nitride.” However, paragraph 69 is a description of fig. 5 which is directed to an example embodiment of a high electron mobility transistor 2. It is unclear if “semiconductor structure 1” should be changed to “high electron mobility transistor 2” or if this entire section is erroneous as there is no passivation layer 300 depicted in fig. 5. Similar errors occur in paragraphs 70, 71, and 72 for the descriptions of figs. 6, 7, and 8 respectively.
Appropriate correction is required.
Claim Objections
Claims 13, 16, 22, and 23 are objected to because of the following informalities:
Regarding claim 13, “wherein said spacer layer comprises Aluminium Nitride;” and “wherein said second active III-N layer comprises Indium Aluminium Nitride;” both use the British English spelling “Aluminium” should be changed to the American English spelling “Aluminum”. Furthermore, “and wherein a thickness of said diffusion barrier layer is lower than 1nm.” Should change “lower than” to “less than” or similar phrasing.
Regarding claim 16, “wherein the thickness of said spacer layer is lower than 2nm.” Should change “lower than” to “less than” or similar phrasing.
Regarding claim 22, “wherein said spacer layer comprises Aluminium Nitride;” and “wherein said second active III-N layer comprises Indium Aluminium Nitride;” both use the British English spelling “Aluminium” should be changed to the American English spelling “Aluminum”. Furthermore, “wherein a thickness of said diffusion barrier layer is lower than 1nm;” should change “lower than” to “less than” or similar phrasing.
Regarding claim 23, “wherein said spacer layer comprises Aluminium Nitride;” and “wherein said second active III-N layer comprises Indium Aluminium Nitride;” both use the British English spelling “Aluminium” should be changed to the American English spelling “Aluminum”. Furthermore, “wherein a thickness of said diffusion barrier layer is lower than 1nm;” should change “lower than” to “less than” or similar phrasing.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 13-19 and 21-24 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yamada (Pub. No. US 2018/0145148 A1).
Regarding claim 13, Yamada teaches a semiconductor structure comprising: a substrate (Fig. 5, substrate 101); an epitaxial III-N semiconductor layer stack on top of said substrate (Fig. 5, substrate 101, nucleation layer 102, channel layer 103, spacer structure 10, barrier layer 104; ¶40-41), said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer (Fig. 5, channel layer 103; ¶42); a spacer layer on top of said first active layer, wherein said spacer layer comprises Aluminum Nitride (Fig. 5, first spacer layer 11; ¶5 & ¶42); a diffusion barrier layer on top of said spacer layer (Fig. 5, second spacer layer 12; ¶42); a second active III-N layer on top of and in direct contact with said diffusion barrier layer, wherein said second active III-N layer comprises Indium Aluminum Nitride (Fig. 5, barrier layer 104; ¶42); with a two-dimensional electron gas between said first active III-N layer and said second active III-N layer (¶4); wherein said diffusion barrier layer comprises Gallium Nitride; and wherein a thickness of said diffusion barrier layer is less than 1nm (Fig. 5, second spacer layer 12; ¶42).
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Regarding claim 14, Yamada further teaches the semiconductor structure wherein said diffusion barrier layer is a monolayer (Fig. 5, second spacer layer 12; ¶42).
Regarding claim 15, Yamada further teaches the semiconductor structure wherein said first active III-N layer comprises Gallium Nitride (Fig. 5, channel layer 103; ¶42).
Regarding claim 16, Yamada further teaches the semiconductor structure wherein, the thickness of said spacer layer is less than 2nm (Fig. 5, first spacer layer 11; ¶42).
Regarding claim 17, Yamada further teaches the semiconductor structure wherein said semiconductor structure further comprises a passivation layer on top of said second active III-N layer (Fig. 5, insulating film 109; ¶43).
Regarding claim 18, Yamada further teaches the semiconductor structure wherein said passivation layer comprises Silicon Nitride and/or an oxide layer (Fig. 5, insulation film 109; ¶43).
Regarding claim 19, Yamada further teaches a high electron mobility transistor wherein said high electron mobility transistor further comprises a gate contact in direct contact with said second active III-N layer in a gate region (Fig. 5, gate electrode 108; ¶40-43).
Regarding claim 21, Yamada further teaches the high electron mobility transistor wherein said high electron mobility transistor further comprises: a source contact contacting said second active III-N layer in a source region (Fig. 5, source electrode 106; ¶43); and/or a drain contact contacting said second active III-N layer in a drain region (Fig. 5, drain electrode 107; ¶43).
Regarding claim 22, Yamada teaches a method for manufacturing a semiconductor structure, wherein said method comprises the steps of: providing a substrate (Fig. 6A, substrate 101); providing an epitaxial III-N semiconductor layer stack on top of said substrate (Fig. 6A, substrate 101, nucleation layer 102, channel layer 103, spacer structure 10, barrier layer 104; ¶44-47); wherein providing said epitaxial III-N semiconducting layer stack comprises the steps of: providing a first active III-N layer (Fig. 6A, channel layer 103; ¶47); providing a spacer layer on top of said first active III-N layer, wherein said spacer layer comprises Aluminum Nitride (Fig. 6A, first spacer layer 11; ¶5, ¶42, & ¶47); providing a diffusion barrier layer on top of said spacer layer, wherein said diffusion barrier layer comprises Gallium Nitride; and where in a thickness of said diffusion barrier layer is less than 1 nm (Fig. 6A, second spacer layer 12; ¶42 & ¶47); providing a second active III-N layer on top of and in direct contact with said diffusion barrier layer; wherein said second active III-N layer comprises Indium Aluminum Nitride (Fig. 6A, barrier layer 104; ¶42 & 47); thereby forming a two-dimensional electron gas between said first active III-N layer and said second active III-N layer (¶4).
Regarding claim 23, Yamada teaches a method for manufacturing a high electron mobility transistor, wherein said method comprises the steps of: providing a substrate (Fig. 6A, substrate 101); providing an epitaxial III-N semiconductor layer stack on top of said substrate (Fig. 6A, substrate 101, nucleation layer 102, channel layer 103, spacer structure 10, barrier layer 104; ¶44-47); wherein providing said epitaxial III-N semiconducting layer stack comprises the steps of: providing a first active III-N layer (Fig. 6A, channel layer 103; ¶47); providing a spacer layer on top of said first active III-N layer, wherein said spacer layer comprises Aluminum Nitride (Fig. 6A, first spacer layer 11; ¶5, ¶42, & ¶47); providing a diffusion barrier layer on top of said spacer layer, wherein said diffusion barrier layer comprises Gallium Nitride; and where in a thickness of said diffusion barrier layer is less than 1 nm (Fig. 6A, second spacer layer 12; ¶42 & ¶47); providing a second active III-N layer on top of and in direct contact with said diffusion barrier layer; wherein said second active III-N layer comprises Indium Aluminum Nitride (Fig. 6A, barrier layer 104; ¶42 & 47); thereby forming a two-dimensional electron gas between said first active III-N layer and said second active III-N layer (¶4); and providing a gate contact in direction contact with said second active III-N layer in a gate region (Fig. 6F, gate electrode 108; ¶52).
Regarding claim 24, Yamada further teaches the method according to claim 22, wherein for providing said diffusion barrier layer on top of said spacer layer a surface temperature is used which is in the range of 725°C to 825°C (¶47).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Nozaki (JP2008198783A).
Regarding claim 20, Yamada teaches the high electron mobility transistor according to claim 19. However, Yamada doesn’t teach the second active III-N layer comprising a recess extending partially through said second active III-N layer in the gate region.
Nozaki teaches the second active III-N layer comprising a recess extending partially through said second active III-N layer in the gate region (Fig. 1, gate electrode 18, electron supply layer 15; ¶17).
Yamada and Nozaki are analogous art as they are in the same field of endeavor of Nitride-based transistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Yamada to incorporate the teachings of Nozaki to have a recess extending partially through the second active III-N layer in the gate region. For the purpose of having normally-off operation of the transistor, as recognized by Nozaki.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kuraguchi (Pub. No. US 2008/0093626 A1), Lim et al. ("Compositional variation of nearly lattice-matched InAlGaN alloys for high electron mobility transistors"), Higashiwaki and Matsui ("InAlN/GaN Heterostructure Field-Effect Transistors Grown by Plasma-Assisted Molecular-Beam Epitaxy"), and Jeganathan et al. ("Lattice-matched InAlN/GaN two-dimensional electron gas with high mobility and sheet carrier density by plasma-assisted molecular beam epitaxy").
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897