DETAILED ACTION
This Office Action is in response to the applicant's application filed January 3rd, 2024. In virtue of this communication, claims 1-19 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 10, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over v.
With respect to claim 1, Murai discloses a power semiconductor device 30 in at least Figs. 1, 6, 17, 18, 21, 22 comprising:
a semiconductor device 30 (see Fig. 1 and paragraph 45-47);
a heat sink 40 (see Fig. 1 and paragraphs 37, 45, 47);
grease 61 (see Figs. 1, 6, 17, 18, and paragraphs 45, 47, 48);
an adhesive 51 (see Figs. 1, 6, 17, 18, and paragraphs 48-55); and
the semiconductor device 30 including a semiconductor element (semiconductor chip), a sealant 31 sealing the semiconductor element (semiconductor chip), and a power terminal 33 electrically connected to the semiconductor element (semiconductor chip) (see Fig. 1 and paragraph 46),
wherein a first area (location of 51) that is a selective area of a lower surface of the semiconductor device 30 is bonded to the heat sink 40 through the adhesive 51 (see Figs. 1, 6, 17, 18, and paragraphs 48-55),
the semiconductor device 30 is in contact with the heat sink 40 through the grease 61 in a second area (location of 61) that is an area other than the selective area of the lower surface of the semiconductor device 30 (see Figs. 1, 6, 17, 18, and paragraphs 45, 47, 48, 52, 53).
Murai does not disclose a terminal block, wherein the terminal block includes an electrode on an upper surface of the terminal block, or wherein the power terminal of the semiconductor device is fastened to the terminal block, and is electrically connected to the electrode of the terminal block.
Nishibori discloses a power semiconductor device in at least Fig. 1 further comprising a terminal block 6, wherein the terminal block 6 includes an electrode (end of 7 for external connection) on an upper surface of the terminal block 6, and wherein a power terminal 7 of a semiconductor device (of 1a, 1b) is fastened to the terminal block 6, and is electrically connected to the electrode of the terminal block 6 (see Fig. 1 and paragraphs 28, 34; 7 mounted to 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the power semiconductor device of Murai would further comprise a terminal block, wherein the terminal block includes an electrode on an upper surface of the terminal block, and wherein the power terminal of the semiconductor device is fastened to the terminal block, and is electrically connected to the electrode of the terminal block as taught by Nishibori because it is well known in the art to combine such power semiconductor devices with resin casings 6 and electrode terminals 7 to surround the power semiconductor device and provide electrical interconnection (see MPEP 2144 I).
With respect to claim 2, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1, wherein the first area (location of 51) is a peripheral area of the lower surface of the semiconductor device 30 (see Murai: Fig. 1 and paragraphs 48, 52-57).
With respect to claim 3, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1, wherein the first area (location of 51) is an area completely surrounding a perimeter of the second area (location of 61) in a plan view (see Fig. 1 and paragraphs 48, 52-57).
With respect to claim 4, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1, further comprising a circuit board (201a, 201b, 201c), wherein the semiconductor device (of 1a, 1b) further includes a signal terminal (8a, 8b) electrically connected to the semiconductor element (1a, 1b), and the signal terminal (8a, 8b) is connected to the circuit board (201a, 201b, 201c) (see Nishibori: Fig. 1 and paragraphs 27, 28; note wires 11a-11c).
With respect to claim 5, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1, wherein the second area (location of 61) protrudes toward the heat sink 40 with respect to the first area (location of 51) on the lower surface of the semiconductor device 30, and a side portion of a step (level difference) between the first area and the second area is covered with the sealant 31 (see Murai: Figs. 17 and 18 and paragraphs 119-122, 125-128).
With respect to claim 7, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1, wherein the sealant (31/39) is exposed on the first area (location of 51), and a second groove (space between 72 and 61) is formed in a portion of the first area (location of 51) on which the sealant (31/39) is exposed, and the adhesive 51 enters the second groove (see Murai: Fig. 18 and paragraphs 124-128).
With respect to claim 10, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1, wherein the terminal block 6 is fastened to the heat sink 3 (see Nishibori: Fig. 1 and paragraphs 28).
With respect to claim 13, the combination of Murai and Nishibori discloses a method for manufacturing the power semiconductor device according to claim 1, the method comprising: preparing the semiconductor device 30 and the heat sink 40; and thermally curing the adhesive 51 to bond the semiconductor device 30 to the heat sink 40 through the adhesive 51 with the semiconductor device 30 being fastened by a clamp fixture (see Murai: Fig. 1 and paragraphs 47-51, 56, 145-150; note 51 cured by heat, also note fastening with bolts).
With respect to claim 14, the combination of Murai and Nishibori discloses a method for manufacturing the power semiconductor device according to claim 1, the method comprising: preparing the semiconductor device 30, the terminal block 6, and the heat sink 40; disposing the semiconductor device 30 on the heat sink 40; and fastening the power terminal 7 to the terminal block 6 with the semiconductor device 30 being disposed on the heat sink 40 and being fastened by a clamp fixture (see Murai: Fig. 1 and paragraphs 47-51, 56, 145-150; note 51 cured by heat, also note fastening with bolts. Also see Nishibori: Fig. 1 and paragraphs 28, 34 and note 7 mounted to 6).
With respect to claim 15, the combination of Murai and Nishibori discloses the method according to claim 14, comprising thermally curing the adhesive 51 to bond the semiconductor device 30 to the heat sink 40 through the adhesive 51 with the semiconductor device 30 being disposed on the heat sink 40 and being fastened by a clamp fixture identical to or different from the clamp fixture (see Murai: Fig. 1 and paragraphs 47-51, 56, 145-150; note 51 cured by heat, also note fastening with bolts).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Murai et al. (US 2016/0276245 A1; hereinafter Murai) in view of Nishibori et al. (US 2011/0298121 A1; hereinafter Nishibori) as applied to claim 1 above, and further in view of Mamitsu et al. (US 2012/0001318 A1; hereinafter Mamitsu).
With respect to claim 6, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1, wherein the sealant 31 is exposed on the second area (location of 61) (see Murai: Fig. 1 and paragraphs 46; note 31 at edges of 32).
The combination does not disclose a first groove is formed in a portion of the second area on which the sealant is exposed, and the grease enters the first groove.
Mamitsu discloses a power semiconductor device in at least Figs. 11A-11B wherein a first groove 400 is formed in a portion of a second area (location of 310) on which a sealant 60 is exposed, and grease 310 enters the first groove 400 (see Figs. 11A-11B and paragraphs 155-158).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the power semiconductor device of the combination of Murai and Nishibori a first groove would be formed in a portion of the second area on which the sealant is exposed, and the grease enters the first groove as taught by Mamitsu because the inclusion of the groove 400 prevents the electrically conducting grease 310 from spreading out of the semiconductor package 100 (see paragraph 156).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Murai et al. (US 2016/0276245 A1; hereinafter Murai) in view of Nishibori et al. (US 2011/0298121 A1; hereinafter Nishibori) as applied to claim 1 above, and further in view of Besshi et al. (WO 2017/221730 A1; hereinafter Besshi; note reference and translation thereof provided as part of IDS dated 01/03/2024).
With respect to claims 8 and 9, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1.
The combination does not disclose wherein the semiconductor element includes a wide-bandgap semiconductor, or wherein the wide-bandgap semiconductor is a SiC semiconductor.
Besshi discloses a power semiconductor device in at least Figs. 3 wherein a semiconductor element (21, 22) includes a wide-bandgap semiconductor, or wherein the wide-bandgap semiconductor is a SiC semiconductor (see Fig. 3 and page 3 first-third paragraphs).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor element of the combination of Murai and Nishibori would include a wide-bandgap semiconductor, wherein the wide-bandgap semiconductor is a SiC semiconductor as taught by Besshi because wide-bandgap semiconductors of SiC are well known in the art and a semiconductor having a large band gap has high allowable current density and low power loss, so that it is possible to operate the semiconductor elements 21 and 22 at high temperature and downsize the semiconductor module 101 (see Besshi: page 3, third paragraph).
Claims 11, 12, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Murai et al. (US 2016/0276245 A1; hereinafter Murai) in view of Nishibori et al. (US 2011/0298121 A1; hereinafter Nishibori) as applied to claims 1 or 14 above, and further in view of Noda et al. (JP 2014/013884 A; hereinafter Noda; note reference and translation thereof provided as part of IDS dated 01/03/2024).
With respect to claim 11, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1.
The combination does not disclose wherein a lower surface of the power terminal in a portion at which the power terminal protrudes from the sealant is higher than an upper surface of the electrode of the terminal block.
Noda discloses a power semiconductor device in at least Fig. 17 wherein a lower surface of a power terminal 302 in a portion at which the power terminal protrudes from a sealant (of 300) is higher than an upper surface of an electrode 306 of a terminal block 303 (see Fig. 17 and paragraphs 22, 66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the power semiconductor device of the combination of Murai and Nishibori a lower surface of the power terminal would be in a portion at which the power terminal protrudes from the sealant is higher than an upper surface of the electrode of the terminal block as taught by Noda because such an electrical connection configuration is a well-known in the art that would have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I).
With respect to claim 12, the combination of Murai and Nishibori discloses the power semiconductor device according to claim 1.
The combination does not disclose wherein fastening the power terminal of the semiconductor device to the electrode of the terminal block presses the semiconductor device to the heat sink.
Noda discloses a power semiconductor device in at least Figs. 17 and 18 wherein fastening a power terminal 302 of an semiconductor device 300 to an electrode 306 of a terminal block 303 presses the semiconductor device 300 to a heat sink 301 (see Figs. 17 and 18 and paragraphs 66, 67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the power semiconductor device of the combination of Murai and Nishibori the fastening the power terminal of the semiconductor device to the electrode of the terminal block would press the semiconductor device to the heat sink as taught by Noda because it is well known to press the heat radiation surface of the back surface of the semiconductor module 300 against the cooler 301 (see Noda: paragraph 66) and such a well-known electrical connection would have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I).
With respect to claim 16, the combination of Murai and Nishibori discloses the method according to claim 14.
The combination does not explicitly disclose fastening the power terminal to the terminal block to press the semiconductor device to the heat sink.
Noda discloses a power semiconductor device in at least Figs. 17 and 18 further comprising fastening a power terminal 302 to a terminal block 303 to press a semiconductor device 300 to a heat sink 301 (see Figs. 17 and 18 and paragraphs 66, 67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the power semiconductor device of the combination of Murai and Nishibori fastening the power terminal to the terminal block would press the semiconductor device to the heat sink as taught by Noda because it is well known to press the heat radiation surface of the back surface of the semiconductor module 300 against the cooler 301 (see Noda: paragraph 66).
With respect to claim 17, the combination of Murai and Nishibori discloses a method for manufacturing the power semiconductor device according to claim 1, the method comprising: preparing the semiconductor device 30, the terminal block 6, and the heat sink 40; disposing the semiconductor device 30 on the heat sink 40; fastening the power terminal 7 to the terminal block 6 with the semiconductor device 30 being disposed on the heat sink 40 (see Murai: Fig. 1 and paragraphs 47-51, 56, 145-150; note 51 cured by heat, also note fastening with bolts. Also see Nishibori: Fig. 1 and paragraphs 28, 34 and note 7 mounted to 6).
The combination does not explicitly disclose fastening the power terminal to the terminal block to press the semiconductor device to the heat sink.
Noda discloses a power semiconductor device in at least Figs. 17 and 18 further comprising fastening a power terminal 302 to a terminal block 303 to press a semiconductor device 300 to a heat sink 301 (see Figs. 17 and 18 and paragraphs 66, 67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the power semiconductor device of the combination of Murai and Nishibori fastening the power terminal to the terminal block would press the semiconductor device to the heat sink as taught by Noda because it is well known to press the heat radiation surface of the back surface of the semiconductor module 300 against the cooler 301 (see Noda: paragraph 66).
With respect to claim 18, the combination of Murai, Nishibori, and Noda discloses the method according to claim 16, wherein the semiconductor device 300 disposed on the heat sink 301 has a clearance between a lower surface of the power terminal 302 and the electrode 306 of the terminal block 303 with no external force being applied to the power terminal 302, before the power terminal 302 is fastened to the terminal block 303 (see Noda: Figs. 17 and 18 and paragraphs 66, 67; note separation between 302 and 306 in Fig. 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor device of the combination Murai and Nishibori disposed on the heat sink would have a clearance between a lower surface of the power terminal and the electrode of the terminal block with no external force being applied to the power terminal, before the power terminal is fastened to the terminal block as taught by Noda because such an electrical connection configuration is a well-known in the art that would have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I).
With respect to claim 19, the combination of Murai, Nishibori, and Noda discloses the method according to claim 17, wherein the semiconductor device 300 disposed on the heat sink 301 has a clearance between a lower surface of the power terminal 302 and the electrode 306 of the terminal block 303 with no external force being applied to the power terminal 302, before the power terminal 302 is fastened to the terminal block 303 (see Noda: Figs. 17 and 18 and paragraphs 66, 67; note separation between 302 and 306 in Fig. 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor device of the combination Murai and Nishibori disposed on the heat sink would have a clearance between a lower surface of the power terminal and the electrode of the terminal block with no external force being applied to the power terminal, before the power terminal is fastened to the terminal block as taught by Noda because such an electrical connection configuration is a well-known in the art that would have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893