Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/11/2024, 06/25/2024,11/12/2024, 03/07/2025,08/19/2025,09/09/2025,09/17/2025, 10/10/2025 and 10/30/2025 being considered by the examiner.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 90-92 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 28-30 of prior U.S. Patent No. US 12446258 B2). This is a statutory double patenting rejection.
Attached here is a table of the claims rejected under statutory double patenting by the claims of the parent case below.
Claim numbering that are statutory double patenting rejection.
Instant Application Claims
Conflicting Application/Patent Claims by Barlage et al, (US 12446258 B2)
1
90. (New) A method of making a thin-film transistor comprising: with a wafer that includes a source and drain positioned at a substrate or insulation layer and a source-channel interfacial member formed in contact with a source contact of the source, using atomic layer deposition to deposit tin oxide to form an n-type semiconductor layer between the source and drain and in contact with the source-channel interfacial member; wherein the source-channel interfacial member is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent the source to reduce leakage current when the thin-film transistor is off.
28. A method of making a thin-film transistor comprising: with a wafer that includes a source and drain positioned at a substrate or insulation layer and a source-channel interfacial member formed in contact with a source contact of the source, using atomic layer deposition to deposit tin oxide to form an n-type semiconductor layer between the source and drain and in contact with the source-channel interfacial member; wherein the source-channel interfacial member is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent the source to reduce leakage current when the thin-film transistor is off.
2
91. (New) The method of claim 90, further comprising using atomic layer deposition to form the source-channel interfacial member
29. The method of claim 28, further comprising using atomic layer deposition to form the source-channel interfacial member.
3
92. (New) The method of claim 90, further comprising: using atomic layer deposition to deposit a gate dielectric layer over the n-type semiconductor layer.
30. The method of claim 28, further comprising: using atomic layer deposition to deposit a gate dielectric layer over the n-type semiconductor layer
And further
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 63-89 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-27 of U.S. Patent No. US 12446258 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claims in US 12446258 B2 teaches the scope of the claim limitations of application 18/576,205 being examined.
Attached here is a table of the claims rejected under double patenting by the claims of the parent case below.
Claim numbering that are anticipated
Instant Application Claims
Conflicting Application/Patent Claims by Barlage et al, (US 12446258 B2)
1
63. (New) A thin-film transistor comprising: a source disposed at a substrate or insulation layer, the source including a source contact; a drain disposed at the substrate or insulation layer and spaced apart from the source; an n-type semiconductor layer extending between the source and drain for formation of a carrier channel between the source and drain, the n-type semiconductor layer including tin oxide; and a source-channel interfacial member positioned between the source contact and the n-type semiconductor layer, the source-channel interfacial member being in contact with the source contact and the n-type semiconductor layer; wherein the source-channel interfacial member and the source contact are functionally analogous to a bipolar junction transistor in a manner that is operable to deplete the carrier channel in a region of the n-type semiconductor layer adjacent the source contact to reduce leakage current when the thin-film transistor is off.
1. A thin-film transistor comprising: a source disposed at a substrate or insulation layer, the source including a source contact; a drain disposed at the substrate or insulation layer and spaced apart from the source; an n-type semiconductor layer extending between the source and drain for formation of a carrier channel between the source and drain, the n-type semiconductor layer including tin oxide; and a source-channel interfacial member positioned between the source contact and the n-type semiconductor layer, the source-channel interfacial member being in contact with the source contact and the n-type semiconductor layer; wherein the source-channel interfacial member is operable to deplete the carrier channel in a region of the n-type semiconductor layer adjacent the source contact to reduce leakage current when the thin-film transistor is off.
2
64. (New) The thin-film transistor of claim 63, wherein the source-channel interfacial member comprises a p-type semiconductor.
2. The thin-film transistor of claim 1, wherein the source-channel interfacial member comprises a p-type semiconductor.
3
65. (New) The thin-film transistor of claim 63, wherein the source-channel interfacial member comprises a p-type metal oxide.
3. The thin-film transistor of claim 1, wherein the source-channel interfacial member comprises a p-type metal oxide.
4
66. (New) The thin-film transistor of claim 63, wherein the source-channel interfacial member comprises oxidized material of the source contact.
4. The thin-film transistor of claim 1, wherein the source-channel interfacial member comprises oxidized material of the source contact.
5
67. (New) The thin-film transistor of claim 63, wherein the source-channel interfacial member comprises a layer of material deposited on the source contact.
5. The thin-film transistor of claim 1, wherein the source-channel interfacial member comprises a layer of material deposited on the source contact.
6
68. (New) The thin-film transistor of claim 63, wherein the source contact comprises ruthenium.
6. The thin-film transistor of claim 1, wherein the source contact comprises ruthenium.
7
69. (New) The thin-film transistor of claim 68, wherein source-channel interfacial member layer comprises ruthenium oxide.
7. The thin-film transistor of claim 6, wherein source-channel interfacial member layer comprises ruthenium oxide.
8
70. (New) The thin-film transistor of claim 63, wherein the source contact comprises cobalt.
8. The thin-film transistor of claim 1, wherein the source contact comprises cobalt.
9
71. (New) The thin-film transistor of claim 70, wherein source-channel interfacial member layer comprises cobalt oxide
9. The thin-film transistor of claim 8, wherein source-channel interfacial member layer comprises cobalt oxide.
10
72. (New) The thin-film transistor of claim 63, wherein the n-type semiconductor layer is formed by atomic layer deposition.
10. The thin-film transistor of claim 1, wherein the n-type semiconductor layer is formed by atomic layer deposition.
11
73. (New) The thin-film transistor of claim 63, further comprising: a gate dielectric layer over the n-type semiconductor layer; and a gate contact over the gate dielectric layer.
11. The thin-film transistor of claim 1, further comprising: a gate dielectric layer over the n-type semiconductor layer; and a gate contact over the gate dielectric layer.
12
74. (New) The thin-film transistor of claim 73, wherein the gate dielectric layer comprises hafnium oxide
12. The thin-film transistor of claim 11, wherein the gate dielectric layer comprises hafnium oxide.
13
75. (New) The thin-film transistor of claim 63, wherein: the drain comprises a drain contact; and the source-channel interfacial member extends between the drain contact and the n-type semiconductor layer, the source-channel interfacial member being in contact with the drain contact.
13. The thin-film transistor of claim 1, wherein: the drain comprises a drain contact; and the source-channel interfacial member extends between the drain contact and the n-type semiconductor layer, the source-channel interfacial member being in contact with the drain contact.
14
76. (New) The thin-film transistor of claim 63, wherein: the drain comprises a drain contact; and the thin-film transistor further comprises another channel interfacial member positioned between the drain contact and the n-type semiconductor layer, the other channel interfacial member being in contact with the drain contact and the n-type semiconductor layer; wherein the other channel interfacial member and the drain contact are functionally analogous to a bipolar junction transistor in a manner that is operable to deplete the carrier channel in a region of the n-type semiconductor layer adjacent the drain contact to reduce leakage current when the thin-film transistor is off.
14. The thin-film transistor of claim 1, wherein: the drain comprises a drain contact; and the thin-film transistor further comprises another channel interfacial member positioned between the drain contact and the n-type semiconductor layer, the other channel interfacial member being in contact with the drain contact and the n-type semiconductor layer.
15
77. (New) A method of making a thin-film transistor comprising: forming a source and drain at a substrate or insulation layer, the drain being spaced apart from the source, the source including a source contact; forming a source-channel interfacial member at the source and in contact with the source contact; and forming an n-type semiconductor layer between the source and drain and in contact with the source-channel interfacial member, the n-type semiconductor layer including tin oxide; wherein the source-channel interfacial member and the source contact are functionally analogous to a bipolar junction transistor in a manner that is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent the source contact to reduce leakage current when the thin-film transistor is off.
15. A method of making a thin-film transistor comprising: forming a source and drain at a substrate or insulation layer, the drain being spaced apart from the source, the source including a source contact; forming a source-channel interfacial member at the source and in contact with the source contact; and forming an n-type semiconductor layer between the source and drain and in contact with the source-channel interfacial member, the n-type semiconductor layer including tin oxide; wherein the source-channel interfacial member is operable to deplete a carrier channel in a region of the n-type semiconductor layer adjacent the source contact to reduce leakage current when the thin-film transistor is off.
16
78. (New) The method of claim 77, wherein the source-channel interfacial member comprises a p-type semiconductor.
16. The method of claim 15, wherein the source-channel interfacial member comprises a p-type semiconductor.
17
79. (New) The method of claim 77, wherein the source-channel interfacial member comprises a p-type metal oxide.
17. The method of claim 15, wherein the source-channel interfacial member comprises a p-type metal oxide
18
80. (New) The method of claim 77, wherein forming the source-channel interfacial member comprises oxidizing material of the source contact.
18. The method of claim 15, wherein forming the source-channel interfacial member comprises oxidizing material of the source contact.
19
81. (New) The method of claim 77, wherein forming the source-channel interfacial member comprises forming a layer of material on the source contact.
19. The method of claim 15, wherein forming the source-channel interfacial member comprises forming a layer of material on the source contact.
20
82. (New) The method of claim 77, further comprising using atomic layer deposition to form the source-channel interfacial member on the source contact.
20. The method of claim 15, further comprising using atomic layer deposition to form the source-channel interfacial member on the source contact.
21
83. (New) The method of claim 77, wherein: the source contact comprises ruthenium; and source-channel interfacial member layer comprises ruthenium oxide.
21. The method of claim 15, wherein: the source contact comprises ruthenium; and source-channel interfacial member layer comprises ruthenium oxide.
22
84. (New) The method of claim 77, wherein: the source contact comprises cobalt; and the source-channel interfacial member layer comprises cobalt oxide.
22. The method of claim 15, wherein: the source contact comprises cobalt; and the source-channel interfacial member layer comprises cobalt oxide.
23
85. (New) The method of claim 77, wherein forming the n-type semiconductor layer comprises using atomic layer deposition to form the n-type semiconductor layer.
23. The method of claim 15, wherein forming the n-type semiconductor layer comprises using atomic layer deposition to form the n-type semiconductor layer
24
86. (New) The method of claim 77, further comprising: forming a gate dielectric layer over the n-type semiconductor layer; and forming a gate contact over the gate dielectric layer.
24. The method of claim 15, further comprising: forming a gate dielectric layer over the n-type semiconductor layer; and forming a gate contact over the gate dielectric layer
25
87. (New) The method of claim 86, wherein the gate dielectric layer comprises hafnium oxide.
25. The method of claim 24, wherein the gate dielectric layer comprises hafnium oxide
26
88. (New) The method of claim 77, further comprising: forming the source-channel interfacial member at the drain and in contact with a drain contact.
26. The method of claim 15, further comprising: forming the source-channel interfacial member at the drain and in contact with a drain contact.
27
89. (New) The method of claim 77, further comprising: forming another channel interfacial member at the drain and in contact with a drain contact; wherein n-type semiconductor layer is formed in contact with the other channel interfacial member; wherein the other channel interfacial member and the drain contact are functionally analogous to a bipolar junction transistor in a manner that is operable to deplete the carrier channel in a region of the n-type semiconductor layer adjacent the drain contact to reduce leakage current when the thin-film transistor is off.
27. The method of claim 15, further comprising: forming another channel interfacial member at the drain and in contact with a drain contact; wherein n-type semiconductor layer is formed in contact with the other channel interfacial member.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897