DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This Office Action is in response to the communication filed on 03 January 2024.
Claims 16-34 are being considered on the merits.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03 Jan 2024, 19 Jan 2024, and 03 Apr 2025 have been considered. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, initialed and dated copies of Applicant's IDS forms 1499 are attached to the instant Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-18, 21-22, 24-27, 30-31, and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Dallaire-Demers, et. al. (US 2021/0272002 A1; hereinafter, Dallaire-Demers) in view of Ostaszewski, et. al. (arXiv:1905.09692v3 [quant-ph] 27 Jan 2021; hereinafter, Ostaszewski), and further in view of Bärtschi, A., Eidenbenz, S. (2019). (“Deterministic Preparation of Dicke States.” In: Gąsieniec, L., Jansson, J., Levcopoulos, C. (eds) Fundamentals of Computation Theory. FCT 2019. Lecture Notes in Computer Science(), vol 11651. Springer, Cham. https://doi.org/10.1007/978-3-030-25027-0_9; hereinafter, “Bartschi”)
Claims 16, 25, and 34:
(Claim 16) A method, implemented by a computing system, the method comprising: (Dallaire-Demers para. 0011: “Embodiments of the present invention include a method of executing a quantum circuit, performed by a quantum computer with a plurality P of subsets S of a plurality of qubits, each of the plurality of subsets comprising at least two qubits”)
(Claim 25) A computing system comprising: processing circuitry and a memory, the memory containing instructions executable by the processing circuitry whereby the computing system is configured to: (Dallaire-Demers para. 0096: “Referring to FIG. 3, a diagram is shown of a hybrid classical quantum computer (HQC) 300 implemented according to one embodiment of the present invention. The HQC 300 includes a quantum computer component 102 (which may, for example, be implemented in the manner shown and described in connection with FIG. 1) and a classical computer component 306. The classical computer component may be a machine implemented according to the general computing model established by John Von Neumann, in which programs are written in the form of ordered lists of instructions and stored within a classical (e.g., digital) memory 310 and executed by a classical (e.g., digital) processor 308 of the classical computer. “)
(Claim 34) A non-transitory computer readable medium storing a computer program product comprising instructions which, when executed on processing circuitry of a computing system, configure the processing circuitry to: (Dallaire-Demers para 0049: “Another embodiment of the present invention is directed to a system comprising a non-transitory computer-readable medium having computer program instructions stored thereon.”)
encode input data into a plurality of physical qubits using an encoding circuit of a Quantum Neural Network (QNN), (Dallaire-Demers, para. 0028 and 0030: “For example, if the quantum computer includes 53 qubits and the encoding of a molecule requires only 40 qubits, then embodiments of the present invention may encode the full ansatz on 53 qubits and measure the expectation value of the Hamiltonian on 40 qubits.” “Embodiments of the present invention may, for example, construct the Hamiltonian from a FermiNet deep neural network.”) the encoding circuit comprising a Y-rotation gate directly followed by a phase gate, the encoding circuit having a circuit depth of two; (Bartschi, pg. 135: “As already introduced in Sect. 3, we use Y-rotation gates to map
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execute a variational ansatz circuit on the physical qubits to generate a classification prediction for at least some of the input data, the variational ansatz circuit comprising a plurality of parameterized gates; (Ostaszewski, pg. 1: “In recent years a lot of progress has been made in improving the performance of parameterized quantum circuits including methods for calculating parameter gradients, hardware efficient ansätze…the authors propose growing the circuit by iteratively adding parameterized gates and re-optimizing the circuit using gradient descent.” Examiner notes Ostaszewski teaches variational quantum eigensolver (VQE)).
reduce a dimensionality of the input data such that a circuit depth of the variational ansatz circuit is reduced below a suitability threshold, wherein the suitability threshold is a circuit depth threshold over which the variational ansatz circuit has a coherence requirement on the physical qubits that cannot be met by a Noisy Intermediate Scale Quantum (NISQ) device. (Bartschi, pg. 127 and 136: “Circuit depth is equivalent to run time and gate count is a measure for overall resource needs. In fact, any difference between gate count and depth can be attributed to gate-level parallelism. Finding minimal-depth circuits is particularly crucial for Noisy Intermediate Scale Quantum (NISQ) devices, which do not allow for full error correction, and thus experience (unwanted) decoherence the longer a computation lasts. Minimizing overall gate count is crucial as each gate operation introduces noise, thus impacting result quality” “Every symmetric pure n-qubit state can be compressed into flog(n + l)l qubits with a circuit of size O(n2 ) and depth O(n) , even on Linear Nearest Neighbor architectures.” Examiner notes Bartschi teaches a minimum suitability threshold in the form of circuit depth and reduction of a circuit depth i.e. dimensionality via compression).
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Ostaszewski into Dallaire-Demers. Dallaire-Demers teaches a quantum computer or a hybrid quantum-classical (HQC) computer leveraging the power of noisy intermediate-scale quantum (NISQ) superconducting quantum processors at and/or beyond the supremacy regime to evaluate the ground state energy of an electronic structure Hamiltonian; Ostaszewski teaches an efficient method for simultaneously optimizing both the structure and parameter values of quantum circuits with only a small computational overhead. One of ordinary skill would have been motivated to combine the teachings of Ostaszewski into Dallaire-Demers in order to optimize NISQ computers using methods for higher tolerance to noise compared to many other quantum algorithms. (Ostaszewski, pg. 1).
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Bartschi into Dallaire-Demers, as modified. Bartschi teaches a deterministic quantum algorithm for the preparation of Dicke states. One of ordinary skill would have been motivated to combine the teachings of Bartschi into Dallaire-Demers, as modified, in order to allow for linear-depth preparation of arbitrary symmetric pure states and – used in reverse – yields a quasilinear-depth circuit for efficient compression of quantum information in the form of symmetric pure states, improving on existing work requiring quadratic depth (Bartschi, abstract).
Claims 17 and 26:
wherein encoding the input data into the plurality of physical qubits comprises encoding two features of the input data for each qubit in the plurality of physical qubits. (Dallaire-Demers, para. 0014: “By parametrizing the pulses used to operate the tunable couplers and the qubit frequencies, it is possible to use the Sycamore device as a variational ansatz. It has been demonstrated experimentally that variational 2-qubit gates can be implemented. Each parametrized two-qubit gate has two components: an exchange term and a tunable dispersive interaction.”)
Claims 18 and 27:
further configured to construct the variational ansatz circuit by combining a first variational ansatz circuit and a second variational ansatz circuit. (Dallaire-Demers, para. 0017: “Embodiments of the present invention may be used to prepare a hardware-efficient ansatz for quantum processors, such as Google's Sycamore quantum processor. For example, embodiments of the present invention may take the class of random circuits that have been used to demonstrate quantum supremacy and modify those circuits to make them into variational circuits. The resulting variational random circuits correspond to specific assignments of variational parameters.” Examiner notes Dallaire-Demers teaches specifically an ansatz circuit for quantum processes and more than one variational circuit).
Claims 21 and 30:
train the QNN to enhance a plurality of parameters used by the parameterized gates of the variational ansatz circuit to generate the classification prediction (Ostaszewski, pg. 1: “For example, these have been demonstrated in chemical simulation, combinatorial optimization, generative modeling and classification [1–8].” “In recent years a lot of progress has been made in improving the performance of parameterized quantum circuits including methods for calculating parameter gradients, hardware efficient ansätze, reducing the number of measurements required, and resolving problems with vanishing gradients”)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Ostaszewski into Dallaire-Demers, as modified, as set forth above with respect to claims 16, 25, and 34, above.
Claims 22 and 31:
training the QNN to enhance the plurality of parameters used by the parameterized gates of the variational ansatz circuit comprises iteratively updating the parameters using a gradient descent to reduce a cost of the parameters (Dallaire-Demers, para. 0026: “After completing the first optimization, embodiments of the present invention may increment the number of layers, initializing the new layers according to some random distribution of parameters and retaining the optimal parameters for the old layers. Embodiments of the present invention may use a small interval of angles such that the identity may be recovered but initial symmetries are broken. New layers and the layers from the previous steps are trained using a numerical optimizer.”)
Claims 24 and 33:
wherein the computing system comprises an NISQ device. (Dallaire-Demers para. 0015: “Embodiments of the present invention are directed to a quantum computer or a hybrid quantum-classical (HQC) computer which leverages the power of noisy intermediate-scale quantum (NISQ) superconducting quantum processors at and/or beyond the supremacy regime to evaluate the ground state energy of the electronic structure Hamiltonian”)
Claims 19 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Dallaire-Demers, in view of Ostaszewski, in view of Bärtschi, and further in view of Alam, et. al. (arXiv:1907.09631v1 [quant-ph] 13 Jul 2019; hereinafter, “Alam”).
Claim 19 and 28:
the variational ansatz circuit has a higher expressibility than each of the first and second variational ansatz circuits individually. (Alam, pg. 3: “For a p-level QAOA, the gates in the PQC with current parameter values are executed sequentially and the output of the quantum processor is measured in the basis state many times to get a distribution…Each QAOA circuit measurement in the basis state generates a candidate solution for the combinatorial optimization problem.”)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Alam into Dallaire-Demers, as modified. Alam teaches the impact of various noise sources on the performance of QAOA. One of ordinary skill would have been motivated to combine the teachings of Alam into Dallaire-Demers, as modified, in order to find and use an optimal p-bound in noisy qubits for superior quantum computing performance. (Alam, pg. 6).
Claims 20 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Dallaire-Demers, in view of Ostaszewski, in view of Bärtschi, and further in view of Yu, et. al. (US 2019/0147359 A1; hereinafter, “Yu”).
Claims 20 and 29:
the variational ansatz circuit has a higher entangling capability than each of the first and second variational ansatz circuits individually. (Yu, para. 0062 and 0092: “Each qubit can be operatively coupled to another qubit through pairs of superconducting couplers 218. That is, during operation of the qubits, the quantum state of a first qubit can be entangled with the quantum state of a second qubit by allowing inductive coupling between the waveguide of the first qubit and the waveguide of the second qubit through a coupler 218.” “Embodiments of the digital and quantum subject matter and the digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly-embodied digital or quantum computer software or firmware, in digital or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them”)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Yu into Dallaire-Demers, as modified. Yu teaches quantum computing devices, including coupling architectures for superconducting flux qubits. One of ordinary skill would have been motivated to combine the teachings of Yu into Dallaire-Demers, as modified, in order to represent and solve a greater range and complexity of problems. (Yu, para. 0032).
Claims 23 and 32:
wherein gradient descent comprises not more than three hyperparameters (Ostaszewski, pg. 1 and 7: “In Ref. [15] the authors propose growing the circuit by iteratively adding parameterized gates and re-optimizing the circuit using gradient descent.” “The exact energy was used to perform updates. The learning rate for Adam was set to 0.05. The hyperparameter for SPSA were the same as in Ref. [10]. Both Rotosolve and Rotoselect converged with significantly fewer energy evaluations than Adam or SPSA.” Examiner notes Ostaszewski teaches gradience descent and one hyperparameter i.e. the learning rate).
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Ostaszewski into Dallaire-Demers, as modified, as set forth above with respect to claims 16, 25, and 34, above.
Prior Art
Xu, et. al. (“Variational Circuit Compiler for Quantum Error Correction”, PHYSICAL REVIEW APPLIED15, 034068 (2021), DOI: 10.1103/PhysRevApplied.15.034068) teaches a variational compiler for efficiently finding the encoding circuit of general quantum error correcting codes with given quantum hardware.
Search Notes
PE2E search notes most relevant: L5 CPC with keywords “quantum” “depth” and “circuit”
Most relevant Google Scholar search: “Y-rotation gate directly followed by a phase gate”
IP.com most relevant search: “quantum variational ansatz circuit Noisy Intermediate Scale Quantum (NISQ) "Y-rotation" gate phase”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sally T. Ley whose telephone number is (571)272-3406. The examiner can normally be reached Monday - Thursday, 10:00am - 6:00pm ET.
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/STL/Examiner, Art Unit 2147
/ERIC NILSSON/Primary Examiner, Art Unit 2151
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